• Journal of Power Electronics
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• v.18 no.6
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.6-12
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• 2024

This paper presents a study on a 2.4GHz differential cascode power amplifier(PA) fabricated using a 130nm CMOS process. This PA is designed for wireless power transmission applications and consists of two differential stages with custom-designed balun transformers for single-ended output. Balun transformers are utilized not only for the output stage but also for power match-ing between each stage. Additionally, a bias circuit with temperature compensation capability is added to maintain stable bias voltage in the 2.4GHz frequency band. As a result, it achieves an output power of 21.75 dBm with a power-added efficiency(PAE) of 40.9% at TT/40℃.

• 전기의세계
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• v.25 no.2
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• pp.65-71
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• 1976

Thyristor 등의 Power Semiconductor에 의한 전자장치를 사용하여 전력의 Conversion, Control 그리고 Switch 등의 기술분야를 Solid State Powerelectronics라고 H.F.Storm는 말하였다. 또 필자는 Thyristor와 전동기제어, System화된 전동기 등에서 Power elecrronics를 언급하고 그 말미를 밝힌 바 있다. Powerelectronics란 전력, 산업용의 Electronics라고 말할 수 있고 광의의 해석에서는 (1)Solid State Power Device에 의한 전력변환, 제어, (2)Computor 및 이에 관련된 응용기술로서의 정보처리의 전력계의 이용, (3)Plasma, Super-Conductor, Laser의 3가지 분야를 말하나 현재로서는 (1)의 분야가 제일 적합하다. 본문에서는 Powerelectronics의 구성요소가 비록 Power에서 Power로 끝나지만 Electronics, Power 및 Control의 3분야의 유기적 형성에서 이루어진다는 것과 이것이 이루어 놓은 업적은 많으나 학문적 체계에는 이 분야의 전문가들의 힘이 커야 한다는 것을 강조하면서 Powerelectronics의 배경에 관해 기술하고자 한다.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.74-77
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• 2002

In this paper we present a novel temperature compensated Hall effect power IC for accurate operation of wide temperature and high current drive of the motor coil. In order to compensate the temperature dependence of Hall sensitivity with negative temperature coefficient(TC), the differential amplifier has the gain consisted of epi-layer resistor with positive TC. The material of Hall device and epi-resistor is epi-layer with the same mobility. The variation of Hall sensitivity is -38% at 150$^{\circ}C$ and 88% at - 40$^{\circ}C$. But the operating point(B$\sub$op/) and release point(B$\sub$RP/) of the Hall power IC are within ${\pm}$25%. The experimental results show very stable and accurate performance over wide temperature range of -40$^{\circ}C$ to 125$^{\circ}C$.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.31-35
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• 2001

IGCTs have established themselves as the power semiconductor of choice at medium voltage levels within the last few years because of their low conduction and switching losses. The trade-off between these losses can be adjusted by various lifetime control techniques and the growing demand for these devices is driving the need for standard types to cover such applications as Static Circuit Breakers (low on-state) and Medium Voltage Drives (low switching losses). The additional demands of Traction (low operating temperatures) and Current Source Inverters (symmetric blocking) would normally result in conflicting demands on the semiconductor. This paper will outline how a range of power devices can meet these needs with a limited number of wafers and gate units. Some of the key differences between IGCTs and IGBTs will be explained and the outlook for device improvements will be discussed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.971-976
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• 2011

This paper proposes a test system for a valve and poles building blocks used for large scale inverters such as STATCOM, SSSC, UPFC and VSC HVDC. Power semiconductors in the valve are normally connected in series to withstand switching voltage much larger than the voltage rating of a single power semiconductor. Therefore, there is a need to verify if the dynamic voltage sharing during switching in a valve is satisfactory. In this paper, we propose a test system that provides the necessary test condition: voltage and current in the valve using resonant circuits. A test scheme for a single phase inverter consisting two poles is also proposed. The performance of the inverter pole has to be verified at the factory test, before the system is installed at the site to secure the reliability of the system. The proposed scheme makes it possible to confirm if the pole can withstand voltage and current switching condition and handle loss.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.34-37
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• 2001

In this paper, we designed and implemented the 60W DC characteristic measurement system for semiconductor devices. The proposed system is composed of 2 SMU(Source and Measure Unit)s, 2 HPU(High power Unit)s, 2VSU(Voltage Source Unit)s, and 2 VMU(Voltage Measurement Unit)s. HPU can source/measure voltage from -200V to 200V and source/measure current from -3A to 3A within 60W. Experimental results show that the implemented system can measure the power devices such as power BJT, regulator IC, and voltage detector.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.21-24
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• 2002

This paper presents a fully integrated, wide tuning range differential CMOS voltage-controlled oscillator, tuned by pMOS-varactors. VCO utilizing a novel tuning scheme is reported. Both coarse digital tuning and fine analog tuning are achieved using pMOS-varactors. The VCO were implemented in a 0.18-fm standard CMOS process. The VCO tuned from 1.8㎓ to 2.55㎓ through 2-bit digital and analog input. At 1.8V power supply voltage and a total power dissipation of 8mW, the VCO features a phase noise of -126㏈c/㎐ at 3㎒ frequency offset.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.59-63
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• 2009

This paper presents two dimensional simulation results of an inductively coupled $Ar/O_2$ plasma reactor. The effects of operating conditions on the plasma properties and the uniformity of atomic oxygen near the wafer were systematically investigated. The plasma density had the linear dependence on the chamber pressure, the flow rate of the feed gas and the power deposited into the plasma. On the other hand, the electron temperature decreased almost linearly with the chamber pressure and the flow rate of the feed gas. The power deposited into the plasma nearly unaffected the electron temperature. The simulation results showed that the uniformity of atomic oxygen near the wafer could be improved by lowering the chamber pressure and/or the flow rate of the feed gas. However, the power deposited into the plasma had an adverse effect on the uniformity.