• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.6
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• pp.99-105
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• 2014

Power transformers are applied throughout the power system to connect systems of different voltage to one another. Since a ratio differential relay offers high sensitivity in detection of internal faults in power transformers, it is widely used in the main protection system. The use of nonlinear devices such as rectifiers and other devices utilizing solid state switching have been increased in industry during recent years. For nonlinear loads, the load current is not proportional to the instantaneous voltage. This situation creates harmonic distortion on the system. The harmonic could differential relay misoperation if not recognized. This paper aims at analyzing and probing into the influences of harmonics on a ratio differential relay for power transformer protection.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.130-136
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• 2015

This study describes the structure and operation modes of vertical stabilization (VS) converter for international thermonuclear experimental reactor (ITER) and proposes a protection method. ITER VS converter supplies voltage (${\pm}1000V$)/current (${\pm}22.5kA$) to superconducting magnets for plasma current vertical stabilization. A four-quadrant operation must be achieved without zero-current discontinuous section. The operation mode of the VS converter is separated in 12-pulse mode, 6-pulse mode and circulation current mode according to the magnitude of the load current. Protection measures, such as bypass and discharge, are proposed for abnormal conditions, such as over current, over voltage, short circuit, and voltage sag. VS converter output voltage is controlled to satisfy voltage response time within 20 msec. Bypass operation is completed within 60 msec and discharge operation is performed successfully. The feasibility of the proposed control algorithm and protection measure is verified by assembling a real controller and implementing a power system including the VS converter in RTDS for a hardware-in-loop (HIL) facility.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1187-1194
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• 2017

After North American wide area black out on August 14, 2003, various studies have been conducted to find out the reason of the disaster. One of main reasons was misoperation of generator protection system. Since then, protective coordination between generator protection system and excitation system controls has been hot issue among electrical engineers. Among various generator protection relays, in this paper, we focused on generator overvoltage and overexcitation relay, which protect the over-flux condition of the generator. Thus, at first, we modeled the generator overvoltage, overexcitation relay and detailed power system including excitation system, governor and etc., based on actual field data. And then, we reviewed the protective coordination of generator overvoltage and overexcitation relay using electromagnetic transient program. In addition, we discussed the protective coordination method for redundant protection relays in both automatic voltage regulator and generator side.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.445-453
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• 2015

A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.23-28
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• 2012

The market of domestic Power Plant Generator Protection and Control System (GPCS) is narrow and required the high reliability, and technology. So, it is still operated as turn-key. In recent years, digital relays has evolved into IED can perform the control and monitoring functions without central monitoring based on IEC61850 international standards communications, and attention for advancement of smart grid and ECMS has been increased in South Korea. The increasing attention on multi-function IED, DGPS(digital generator protection system), for internal fault protection of large generator results in starting a national project in South Korea, the IED prototype development for next-generation power units. The voltage restrained overcurrent relay have been used as back-up overcurrent protection for generators. In this paper, voltage restrained overcurrent relay is one of the back-up protective factors in generator protection IED was presented. For evaluation performance of the voltage restrained overcurrent relay, the data of ATPDraw5.7p4 modeling was used.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2089-2098
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• 2017

Microgrid is a convenient, reliable, and eco-friendly approach for the integration of Distributed Generation (DG) sources into the utility power systems. To date, AC microgrids have been the most common architecture, but DC microgrids are gaining an increasing interest owing to the provision of numerous benefits in comparison with AC ones. These benefits encompass higher reliability, power quality and transmission capacity, non-complex control as well as direct connection to some DG sources, loads and Energy Storage Systems (ESSs). In this paper, main challenges and available approaches for the protection of AC and DC microgrids are discussed. After description, analysis and classification of the existing schemes, some research directions including coordination between AC and DC protective devices as well as development of combined control and protection schemes for the realization of future hybrid AC/DC microgrids are pointed out.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1063-1064
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• 2008

In this paper, two kinds of the protection circuits are proposed and simulated to verify their performances. One is an over current protection circuit, and the other is a no load protection circuit which reduces power consumption. These protection circuits of an LED drive circuit can reduce power consumption and prevent to damage the elements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.64-70
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• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.348-350
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• 2003

In recent years, with the continuous development of modem power system, the need for high performance protection to meet the customers' requests for more stable and reliable power supply has become increasingly emphasized. So, there is urgent need for a proper testing platform about not only existing digital protection relay but also new digital protection relay on the transmission line. It is also dynamic-state test which can test the performance of digital relay. This paper suggests basic system model for testing transmission line protection using PSCAD/EMTDC, and presents the process of the component modeling in the basic system.