• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.367-373
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• 2001

A programmable A/D converter is designed with 8 N and P channel MOSFETs, respectively. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a 1.2 ${\mu}{\textrm}{m}$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10m Volt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, 37㎽ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.40-45
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• 1991

It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.

• ETRI Journal
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• v.35 no.4
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• pp.632-637
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• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Journal of the Korean Society of Industry Convergence
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• v.27 no.4_2
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• pp.935-942
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• 2024

This study analyzes the effects of the parasitic capacitance of the SiC MOSFET used in the Dual Active Bridge ( DAB) converter and proposes a method for calculating the leakage inductance of the transformer. The DAB converter employs high-frequency switching to achieve high efficiency, high power density, and reliability. MOSFETs possess parasitic capacitance, which induces resonance with the leakage inductance of the transformer during switching operations, resulting in a voltage change delay. This paper discusses the effect of the delay of voltage changes on the DAB converter output and proposes a method to calculate the delay time. This method aims to equalize the delay time to minimize this effect and enhance the accuracy of the leakage inductance calculation of the transformer. The proposed method is validated through experiments and simulations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.54-65
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• 1999

As the integration ratio and operating speed increase, it has become an important problem to estimate the dissipated power during the design procedure to reduce th TTM(time to market). This paper proposed a prediction model for the maximum dissipated power of a CMOS logic gate. This model uses a calculating method. It was constructed by including the characteristics of MOSFETs, the operational characteristics of the gate, and the characteristics of the input signals. As the construction procedure, a maximum power estimation model for CMOS inverter was formed first, And then, a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. We designed several CMOS gates in layout level with $0.6{\mu}m$ design rule to apply both to HSPICE simulation and to the proposed models. The comparison between the two results showed that the gate conversion model and the power estimation model had within 5% and 10% of the relative errors, respectively. Those values show that the proposed models have sufficient accuracies. Also in calculation time, the proposed models were more than 30 times faster than HSPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.504-510
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• 2017

This paper presents an AC-DC power module design and evaluates its efficiency and reliability when used for electronics appliances. This power module consists of a PWM control IC, power MOSFETs, a transformer and several passive devices. The module was tested at an input voltage of 220V (RMS) (frequency 60 Hz). A test was conducted in order to evaluate the operation and power efficiency of the module, as well as the reliability of its protection functions, such as its over-current protection (OVP), overvoltage protection (OVP) and electromagnetic interference (EMI) properties. Especially, we evaluated the thermal shut-down protection (TSP) function in order to assure the operation of the module under high temperature conditions. The efficiency and reliability measurement results showed that at an output voltage of 5 V, the module had a ripple voltage of 200 mV, power efficiency of 73 % and maximum temperature of $80^{\circ}C$ and it had the ability to withstand a stimulus of high input voltage of 4.2 kV during 60 seconds.