• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.793-796
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• 2003

The electronics of a mobile robot ill nuclear facilities is required to satisfied the reliability to sustain survival in its radiation environment. To know how much radiation the robot has been encountered to replace sensitive electronic parts, a dosimeter to measure total accumulated dose is necessary. Among many radiation dosimeters or detectors, semiconductor radiation sensors have advantages in terms of power requirements and their sires over conventional detectors. This paper describes the use of the radiation-induced threshold voltage change of a commercial power pMOSFET as an accumulated radiation dose monitoring mean and that of the photo-current of a commercial PIN Diode as a dose-rate measurement mean. Commercial p-type power MOSFETs and PIN Diodes were tested in a Co-60 gamma irradiation facility to see their capabilities as radiation sensors. We found an inexpensive commercial power pMOSFET that shows good linearity in their threshold voltage shift with radiation dose and a PIN diode that shows good linearity in its photo-current change with dose-rate. According to these findings, a radiation hardened hybrid electronic radiation dosimeter for nuclear robots has been developed for the first time. This small hybrid dosimeter has also an advantage in the point of view of reliability improvement by using a diversity concept.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.376-379
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• 2021

The design and performance of a SiC-MOSFET-based 11-kW bi-directional on-board charger (OBC) for electric vehicles is presented. The OBC consists of a three-phase two-level AC/DC converter and a CLLLC resonant converter. All the power devices are implemented with SiC-MOSFETs to reduce the conduction losses generated in the OBC, and the DC-link voltage is designed to track the level of battery voltage in the forward and reverse powering modes. As a result, the CLLLC resonant converter always runs at the switching frequency near the resonant frequency, resulting in high-efficiency operation at the maximum powering modes. As the DC-link voltage varies according to the battery voltage, the AC/DC converter in the proposed OBC adopts an adaptive DC-link voltage controller. The performance of the proposed 11-kW OBC is verified by a prototype converter with the following specifications: three-phase 60-Hz 380-V input, 11-kW capacity, and battery voltage range of 214-413-V, resulting in the conversion efficiency of over 95.0-% in the forward and reverse powering modes.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• Journal of Power Electronics
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• v.14 no.1
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• pp.30-39
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• 2014

This paper studies a new three-level pulse-width modulation (PWM) resonant converter for high input voltage and high load current applications. In order to use high frequency power MOSFETs for high input voltage applications, a three-level DC converter with two clamped diodes and a flying capacitor is adopted in the proposed circuit. For high load current applications, the secondary sides of the proposed converter are connected in parallel to reduce the size of the magnetic core and copper windings and to decrease the current rating of the rectifier diodes. In order to share the load current and reduce the switch counts, three resonant converters with the same active switches are adopted in the proposed circuit. Two transformers with a series connection in the primary side and a parallel connection in the secondary side are adopted in each converter to balance the secondary side currents. To overcome the drawback of a wide range of switching frequencies in conventional series resonant converters, the duty cycle control is adopted in the proposed circuit to achieve zero current switching (ZCS) turn-off for the rectifier diodes and zero voltage switching (ZVS) turn-on for the active switches. Finally, experimental results are provided to verify the effectiveness of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.5
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• pp.434-441
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• 2016

This paper deals with transformer turns ratio design with the consideration of loss minimization in isolated bidirectional DC-DC converter. Generally, the rms value of current, magnitude of current at switching instance, and duty ratio of a converter vary according to the turns ratio of an isolation transformer in the converter under the same voltages and output power level. Therefore, the transformer turns ratio has an effect on the total loss in a converter. The switching and conduction losses of IGBTs and MOSFETs consisting of dual-active bridge converter are analyzed, and iron and copper losses in an isolation transformer and inductor are calculated. Total losses are calculated and measured in cases of four different transformer turns ratios through simulation and experiment with 3-kW converter, and an optimum turns ratio that provides minimum losses is found. The usefulness of the proposed transformer turns ratio design approach is verified through simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1131-1137
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• 2015

Gallium nitride (GaN) is a promising material for next-generation high-power applications due to its wide bandgap, high breakdown field, high electron mobility, and good thermal conductivity. From a structure point of view, the vertical device is more suitable to high-power applications than planar devices because of its area effectiveness. However, it is challenging to obtain a completely upright vertical structure due to inevitable sidewall slope in anisotropic etching of GaN. In this letter, we design and analyze the enhancement-mode n-channel vertical GaN MOSFET with variation of sidewall gate angle by two-dimensional (2D) technology computer-aided design (TCAD) simulations. As the sidewall slope gets closer to right angle, the device performances are improved since a gradual slope provides a leakage current path through the bulk region.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.427-435
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• 2014

Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.