• Title/Summary/Keyword: Power Control Error

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인버터의 전류측정 오차에 기인하는 교류전동기의 토크리플 저감 (Reduction of Torque Ripple due to Current-Sensing Errors in Inverter-Fed AC Motor Systems)

  • 윤덕용;홍순찬
    • 전력전자학회논문지
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    • 제3권4호
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    • pp.280-286
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    • 1998
  • 본 논문에서는 벡터제어방식의 인버터에 의하여 구동되는 교류전동기 제어 시스템에서 전류특정회로에서의 측정오차에 기인하는 전동기의 토크리플을 저감하는 방법을 제안한다. 2상의 전류를 측정하는 회로에서의 오프셋 전압과 전압증폭률이 서로 다를 때 전동기 출력토크에 발생되는 리플을 각각 정량적으로 분석하고, 이로부터 온라인 상태에서 실시간으로 토크리플을 제거할 수 있는 알고리즘을 제시하였다. 제안된 방식의 유용성을 확인하기 위하여 이를 영구자석형 동기전동기에 적용하였을 경우에 대하여 출력토크의 리플을 계산하고 이를 제거하는 알고리즘을 컴퓨터로 시뮬레이션하였다.

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Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices

  • Gookyi, Dennis Agyemanh Nana;Ryoo, Kwangki
    • Journal of Information Processing Systems
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    • 제15권6호
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    • pp.1406-1421
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    • 2019
  • The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

콘크리트 믹서 트럭용 믹서 감속기의 차동 유성 기어 트레인에 대한 위험속도 해석 (The Critical Speed Analysis of the Differential Planetary Gear Train of a Concrete Mixer Truck Mixer Reducer)

  • 배명호;배태열;김당주
    • 드라이브 ㆍ 컨트롤
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    • 제14권1호
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    • pp.1-7
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    • 2017
  • The power train of a concrete truck mixer reducer includes differential planetary gears to get a large reduction ratio for operating the mixer drum in a compact structure. These differential planetary gears are a very important part of the mixer reducer where strength problems are the main concern. Gear bending stress, gear compressive stress and scoring failure are the main concerns. Many failures in differential planetary gears are due to the insufficient gear strength and resonance problems caused by major excitation forces such as gear mating failure in the transmission. In the present study, where the excitation frequencies are the gear tooth passing frequencies of the mating gears, a Campbell diagram is used to calculate differential planetary gear critical speeds. Mode shapes and natural frequencies of the differential planetary gears are calculated by CATIA V5. These are used to predict gear resonance failures by comparing the working speed range with the critical speeds due to the gear transmission errors of the differential planetary gears.

Harmonic Identification Algorithms Based on DCT for Power Quality Applications

  • Yepes, Alejandro G.;Freijedo, Francisco D.;Doval-Gandoy, Jesus;Sanchez, Oscar Lopez;Fernandez-Comesana, Pablo;Alvarez, Jano Malvar
    • ETRI Journal
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    • 제32권1호
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    • pp.33-43
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    • 2010
  • The increasing demand for non-sinusoidal currents affects the quality of distribution networks. Harmonic detection is a crucial step in the cancellation of those components by active power filters. In this paper, the discrete cosine transform (DCT) is compared with different implementations based on Fourier transforms, demonstrating their equivalences and the advantages provided by the former. We demonstrate that the phase error in the presence of grid frequency deviations and the transient length are reduced by half in comparison to the discrete Fourier transform. A novel algorithm is developed to provide frequency adaptation to the DCT, taking advantage of its good features. The window width is adjusted in real time according to the actual value of the grid fundamental frequency by means of a phase-locked loop. A technique based on dithering is employed to overcome the limitation caused by the truncation of the window number of samples, so the frequency resolution is enhanced. The theoretical approach is verified by simulated and experimental results.

자기부상열차용 DC-DC 전원장치에 관한 연구 (A Study on DC-DC Power Supply for Maglev)

  • 정춘병;조주현;조정민;전기영;이상집;오봉환;이훈구;한경희
    • 한국조명전기설비학회:학술대회논문집
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    • 한국조명전기설비학회 2004년도 춘계학술대회 논문집
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    • pp.347-352
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    • 2004
  • The author present a modified multi-loop algorithm including feedforward for controlling a 55kW step down chopper in the power supply of Maglev. The control law for the duty cycle consists of three terms. The first is the feedforward term which compensates for variations in the input voltage. The second term consists of the difference between the slowly moving inductor current and output current. The third term consists of proportional and integral terms involving the perturbation in the output voltage. This perturvation is derived by subtracting the desired output voltage from the actual output voltage. The proportional and integral action stabilizes the system and minimizes output voltage error. In order to verify the validity of the proposed multi-loop controller, simulation study was tried using Matlab simulink.

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다중 제어루프에 의한 DC-DC 전원장치에 관한 연구 (A Study on DC-DC Power Supply with a Multi-loop Controller)

  • 조주현;정정훈;조정민;김길동;이승환;이훈구;김용주;한경희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 하계학술대회 논문집 B
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    • pp.1262-1264
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    • 2003
  • The author Present a modified multiloop algorithm including feedforward for controlling a 45kW step down chopper in the power supply of Maglev. The control law for the duty cycle consists of three terms. The first is the feedforward term which compensates for variations in the input voltage. The second term consists of the difference between the slowly moving inductor current and output current. The third term consists of proportional and integral terms involving the perturbation in the output voltage. This perturvation is derived by subtracting the desired output voltage from the actual output voltage. The proportional and integral action stabilizes the system and minimizes output voltage error. To verify the validity of the proposed multiloop controller, simulation study was tried using Matlab/sirnulink.

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가중치를 고려한 슬라이딩 모드 제어기 설계 (Sliding Mode Controller Design Considering Weight)

  • 임동균;서병설
    • 전력전자학회논문지
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    • 제4권3호
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    • pp.223-230
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    • 1999
  • 일반적인 슬라이딩 모드 제어기 동조 방법은 동조 피라미터의 수가 플랜트의 차수에 비례하기 때문에 고차의 프로세스에서는 어렵고, 실용적이지 못하다. Camacho(1996)은 고차의 프로세스를 시간 지연 항이 포함된 1차 프로세스로 모델링한 고정 구조 슬라이딩 모드 제어기 설계 방법을 제안하였다. 그러나 Camacho가 제안한 방법은 시간 지연 항을 1차 Taylor 급수로 근사화하는 과정에서 발생되는 근사 오차에 의해 오버슈트, 정착시간, 명령추종 등에 문제점이 있다. 본 논문에서는 이를 개선하기 위해 가중치를 고려한 새로운 형태의 Taylor 근사 기법과 이를 토대로 새로운 슬라이딩 모드 제어기 설계 방법을 제안하고자 한다.

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자기부상열차용 DC-DC 전원장치에 관한 연구 (A Study on DC-DC Power Supply for Magnetically Levitated Vehicle)

  • 정춘병;전기영;이훈구;한경희
    • 조명전기설비학회논문지
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    • 제18권6호
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    • pp.128-135
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    • 2004
  • 본 논문은 자기부상열차용 전원의 문제점을 개선시키기 위해서 다중루프 제어기를 제시하였다. 제시된 제어기는 3개의 부분으로 구성되어 있다. 첫 번째는 입력전압의 변동에 대하여 보상할 수 있는 Feed Forward제어기이며 두 번째는 리액터 전류와 출력 전류의 차를 보상하며, 세 번째는 비례적분제어기를 사용하여 출력전압에 포함된 리플을 감소시키므로써, 안정화된 시스템을 구현하였다. 이 시스템의 특성을 확인하기 위해서 Matlab Simulink와 고성능 DSP소자인 TMS320F240을 이용하여 비교 분석하였다.

스마트 사물인터넷 기기용 저리플 방식의 스텝다운 컨버터 분석 (Analysis of Step-Down Converter with Low Ripple for Smart IoT Devices)

  • 김다솔;알라딘;구진선;쿠마르;송한정
    • 한국산업융합학회 논문집
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    • 제24권5호
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    • pp.641-644
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    • 2021
  • Wearable devices and IoT are being utilized in various fields, where all systems are developing in the direction of multi-functionality, low power consumption, and high speed. In this paper, we propose a DC -DC Step-down C onverter for IoT smart devices. The proposed DC -DC Step-down converter is composed of a control block of the power supply stage. It also consists of an overheat protection circuit, under-voltage protection circuit, an overvoltage protection circuit, a soft start circuit, a reference voltage circuit, a lamp generator, an error amplifier, and a hysteresis comparator. The proposed DC-DC converter was designed and fabricated using a Magnachip / Hynix 180nm CMOS process, 1-poly 6-metal, the measured results showed a good match with the simulation results.

8.2-GHz band radar RFICs for an 8 × 8 phased-array FMCW receiver developed with 65-nm CMOS technology

  • Han, Seon-Ho;Koo, Bon-Tae
    • ETRI Journal
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    • 제42권6호
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    • pp.943-950
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    • 2020
  • We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.