• Journal of Korea Society of Digital Industry and Information Management
• /
• v.5 no.3
• /
• pp.69-75
• /
• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.2
• /
• pp.193-199
• /
• 2011

In this paper, we proposed battery driven low power algorithm in mobile device. Algorithm the mobile devices in power of the battery for the task to perform power consumption to reduce the frequency alters. Power of the battery perform to a task power consumption of is less than the task perform to frequency the lower. Frequency control the task, depending on in the entire system devices used among the highest frequency with devices first target perform to. Frequency in the decrease the second largest frequency with of the device the frequency in changes the power consumption to calculate. The calculated consumption power the battery of level is greater than level the frequency by adjusting power consumption, lower power of the battery the task perform when you can to the frequency to adjust. Experiment the frequency by adjusting power consumption a method to reduce using [6] and in the same environment power of the battery consider the task to perform frequency were controlled. The results in [6] perform does not battery power on task operates that the result was.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.11
• /
• pp.1596-1602
• /
• 2021

Battery-operated IoT devices in IoT systems require low power consumption. In general, IoT devices enter a sleep state synchronously to reduce power consumption. A problem arises when an IoT device has to handle asynchronous user requests, as the duty cycle must be reduced to enhance response time. In this paper, we propose a new low-power-consumption scheme, called Repetitive Wake-up scheme for IoT systems of asynchronous environments such as indoor lights control. The proposed scheme can reduce power consumption by sending wake-up signals from the smartphone repetitively and by retaining the IoT device in sleep state to the smallest possible duty cycle. In the various environments with IoT devices at home or office space, we showed that the proposed scheme can reduce power consumption by up to five times compared to the existing synchronous interlocking technique.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.7
• /
• pp.3351-3369
• /
• 2017

In recent years, datacenters, network devices and computers have proliferated. The power consumed by information and communication technology (ICT) devices has inflated in an extraordinary manner. Green communication has emerged as a new approach to reduce and optimize power consumption in ICT sector. Many methods and protocols have been proposed and implemented to achieve green communication. Nevertheless, the increase of power consumption remains a problem. In this work, we attempt to reduce and optimize power consumption of network devices in datacenters environment utilizing software defined network (SDN) paradigm. To gain more insight of the power consumption requirements of network switches, a power measurement system is constructed to measure power consumption levels of network devices. Subsequently, we propose a duplication resolver algorithm (DRA) to power off/on switches reactively. DRA algorithm reduces the required time by switches to construct their flow tables after rebooting. To this end, DRA-based external circuit has been constructed utilizing Ethernet module and an Arduino kit to control power supplies of network devices. To facilitate our work, a testbed has been constructed utilizing Ryu SDN controller, HP2920-24G switches and Arduino kits. Our results show that DRA algorithm can reduce both the power usage and start-up time delay of network switches after failures.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.16 no.2
• /
• pp.61-68
• /
• 2020

Nuclear power plants have a lower cost of power generation, and they are more eco-friendly than other power generation plants. Also, we need to prepare nuclear plant accidents because of their severe damage. In the event of a safety accident, such as a radiation leak, by applying a wireless sensor network to a nuclear power plant, many sensor nodes can be used to monitor radiation and transmit information to an external base station to appropriately respond to the accident. However, applying a wireless sensor network to nuclear power plants requires routing protocols that consider the sensor network size and bypass obstacles such as plant buildings. In general, the hierarchical-based routing protocols are efficient in energy consumption. In this study, we look into the problems that may occur if hierarchical-based routing protocols are applied to nuclear power plants and propose improved routing protocols to solve these problems. Simulation results show that the proposed routing protocol is more effective in energy consumption than the existing LEACH protocol.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
• /
• v.10 no.2
• /
• pp.74-79
• /
• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.749-752
• /
• 2012

Recent social issues is energy issues, green computing has attracted attention. Active research on the power consumption of computer profiling is one of the various approaches for green computing. As a representative tool PowerAPI, PowerTop, JouleMeter, pTop, and EnergyChecker. These studies can be used to measure the power consumption of each computer device because it is based on a pure software. Based on this profiling process at the level of power consumption by performing the power consumption of each program can be analyzed. Therefore to identify the processes that consume a lot of power and control the total power consumption by reducing, also when designing the program, based on data profiling power enables the design of low-power programs, and ultimately can be oriented green computing. In this paper, by comparing and analyzing the associated representative studies, the ideal process level will draw on the characteristics of the power consumption profiler.

• Journal of information and communication convergence engineering
• /
• v.10 no.1
• /
• pp.78-84
• /
• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.8
• /
• pp.1569-1580
• /
• 2016

For the 2.4 GHz active RFID to be successful in the market, one of the requirements is the increased battery life. However, currently we do not have any accurate power consumption estimation method. In this study we develop a simulation model, which can be used to estimate power consumption of tag accurately. Six different simulation models are proposed depending on collision algorithm and query command method. To improve estimation accuracy, we classify tag operating modes as the wake-up receive, UHF receive, sleep timer, tag response, and sleep modes. Power consumption and operating time are identified according to the tag operating mode. Query command for simplifying collection and ack command procedure and newly developed collision control algorithm are used in the simulation. Other performance measures such as throughput, recognition time for multi-tags, tag recognition rate including power consumption are compared with those from the current standard ISO/IEC 18000-7.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.3
• /
• pp.167-181
• /
• 2001

A stepwise driving method was used for reducing the AC power consumption in a TFT-LCD. The AC power takes the largest portion of the total power consumption of a TFT-LCD. Experimental results confirmed that the AC power saving efficiency reached up to 75% when a 5-stepwise driving with each step time of $2\mu$ sec was applied to a 14.1 inch-diagonal XGA TFT-LCD. The second largest component of power consumption called the DC power comes from the quiescent currents in Op-amps. A simple and efficient architecture was proposed in this work to reduce this DC power consumption: Half of the Op-amps have the 5V-supplies, and the rest half have the 10V-supplies, and two Op-amps are shared by adjacent two channels. Measurements of test circuits showed that this simple method could reduce over 40% of the DC power consumption..