• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Korea institute for structural maintenance and inspection
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• v.15 no.1
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• pp.120-128
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• 2011

Recently, safety diagnosis of the existing structures has been emerged as important issue. In particular, systematical and precise safety diagnostics for steel structures for power substation, have been required. Steel structures for power substation are under the periodical impact loads from operations of gas insulated switchgear. These loading condition accelerates damage and aging of structure. The objective of this research is to evaluate damage of structure under periodical impact loads. To evaluate the integrity of structures as organizing mathematical models including the dynamic characteristics of structures, Frequency Domain Decomposition method was choiced and an algorism was proposed. For verifying this methods and algorism, a mathematical model is composed of the development of a variety of reverse analysis and a signal processing technology reflecting physical damage of structures. A series of analysis and test results indicatge that proposed method has a confidence for applying a filed test. Therefore, it is expected to be able to take advantage of system identification to detect damage for the maintenance and management of steel structures under periodical impact loads such as power substation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.199-205
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• 2007

In this paper, a novel hexagonal-shaped electromagnetic bandgap(EBG) power plane for the suppression of the ground bounce noise(GBN) in high-speed circuits is proposed. The proposed structure consists of hexagonal-shaped unit cells and detoured bridges connecting the unit cells. The hexagonal-shaped unit cells could omni-directionally suppress the GBN in digital circuits. The fabricated power plane's omni-directional -30 dB suppression bandwidth is from 330 MHz to 5.6 GHz. Then the proposed structure suppresses electromagnetic interference(EMI) caused by the GBN within the stopband. As a result, the proposed structure is expected to be conducive solving EMI problem in high-speed circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.71-80
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• 2004

A new SSN(Simultaneous Switching Noise) model is presented, which can afford to investigate SSN due to integrated circuit package. It is shown that previous SSN models are not accurate enough to be practical since they do not take decoupling capacitor into account. In this paper, a new SSN model including the decoupling capacitor is developed. It is verified that the model has excellent agreement(within $5\%$ error) with HSPICE simulation which employs TSMC 0.18um CMOS process technology.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.139-141
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• 2006

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Nuclear Engineering and Technology
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• v.51 no.3
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• pp.723-730
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• 2019

Acquiring instrumentation signals generated from nuclear power plants (NPPs) is essential to maintain nuclear reactor integrity or to mitigate an abnormal state under normal operating conditions or severe accident circumstances. However, various safety-critical instrumentation signals from NPPs cannot be accurately measured on account of instrument degradation or failure under severe accident circumstances. Reactor vessel (RV) water level, which is an accident monitoring variable directly related to reactor cooling and prevention of core exposure, was predicted by applying a few signals to deep neural networks (DNNs) during severe accidents in NPPs. Signal data were obtained by simulating the postulated loss-of-coolant accidents at hot- and cold-legs, and steam generator tube rupture using modular accident analysis program code as actual NPP accidents rarely happen. To optimize the DNN model for RV water level prediction, a genetic algorithm was used to select the numbers of hidden layers and nodes. The proposed DNN model had a small root mean square error for RV water level prediction, and performed better than the cascaded fuzzy neural network model of the previous study. Consequently, the DNN model is considered to perform well enough to provide supporting information on the RV water level to operators.

• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.21-29
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• 1996

Industrial equipment, such as power plant, is required to operate reliably, continuously and economically under rather severe conditions of temperature, stress, and enbironment. To test structural integrity and fitness, ultrasonic nondestructive testing is used because of effectiveness and simplicity. In this paper, wavelet transform based least mean square(LMS) algorithm is applied to reduce the influence of the interference occurring between randomly positioned small scatters. The RUN test is performed to check the nonstationarity of the speckle noise signal. The performance of this new approach is compared with that of the time domain LMS algorithm by means of condition numbers, signal-to-noise ratio and 3-D image. As a result, the wavelet transform based LMS algorithm shows better performance than the time domain LMS algorithm in this experiment.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.32 no.3A
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• pp.183-188
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• 2012

The bonded tendon was adopted to the reactor containment building of some operating nuclear power plants in Korea and the assessment of the prestress force on the bonded tendon is very important for the evaluation of the structural integrity. The prestress force of the bonded tendon at real reactor containment building, was evaluated using the SI technique and impact signal analysis technique which were developed to improve the existing indirect assessmment technique. For these techniques, the strain of the reactor containment building and the stress wave velocity of the bonded tendon were measured. Both SI technique and impact signal analysis technique give the highly reliable results comparison with the existing theoretical approach. Therefore, it is confirmed that the developed techniques are very useful for the evaluation of the prestress force on the bonded tendon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.