• Journal of the Korean Society for Precision Engineering
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• v.23 no.6 s.183
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• pp.166-173
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• 2006

In this study, a probe array has been developed for use in a data storage device that is based on scanning probe microscope (SPM) and MEMS technology. When recording data bits by poling the PZT thin layer and reading them by sensing its piezoresponse, commercial probes of which the tip heights are typically shorter than $3{\mu}m$ raise a problem due to the electrostatic forces occurring between the probe body and the bottom electrode of a medium. In order to reduce this undesirable effect, a poly-silicon probe with a high aspect-ratio tip was fabricated using a molding technique. Poly-silicon probes fabricated by the molding technique have several features. The tip can be protected during the subsequent fabrication processes and have a high aspect ratio. The tip radius can be as small as 15 nm because sharpening oxidation process is allowed. To drive the probe, electrostatic actuation mechanism was employed since the fabrication process and driving/sensing circuit is very simple. The natural frequency and DC sensitivity of a fabricated probe were measured to be 18.75 kHz and 16.7 nm/V, respectively. The step response characteristic was investigated as well. Overshoot behavior in the probe movement was hardly observed because of large squeeze film air damping forces. Therefore, the probe fabricated in this study is considered to be very useful in probe-based data storages since it can stably approach toward the medium and be more robust against external shock.

• Korean Journal of Metals and Materials
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• v.46 no.2
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• pp.69-79
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• 2008

A composition consisting of 10 nm-Ni/1 nm-Pd/(30 nm or 70 nm-poly)Si was thermally annealed using rapid thermal for 40 seconds at $300{\sim}1100^{\circ}C$ to improve the thermal stability of conventional nickel monosilicide. The annealed bilayer structure developed into $Ni(Pd)Si_x$, and the resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness were investigated. The silicide, which formed on single crystal silicon, could defer the transformation of $NiSi_2$, and was stable at temperatures up to $1100^{\circ}C$. It remained unchanged on polysilicon substrate compared with the sheet resistance of conventional nickel silicide. The silicides annealed at $700^{\circ}C$, formed on single crystal silicon and 30 nm polysilicon substrates exhibited 30 nm-thick uniform silicide layers. However, silicide annealed at $1,000^{\circ}C$ showed preferred and agglomerated phase. The high resistance was due to the agglomerated and mixed microstructures. Through X-ray diffraction analysis, the silicide formed on single crystal silicon and 30 nm polysilicon substrate, showed NiSi phase on the entire temperature range and mixed phases of NiSi and $NiSi_2$ on 70 nm polysilicon substrate. Through scanning probe microscope (SPM) analysis, we confirmed that the surface roughness increased abruptly until 36 nm on 30 nm polysilicon substrate while not changed on single crystal and 70 nm polysilicon substrates. The Pd-inserted nickel monosilicide could maintain low resistance in a wide temperature range and is considered suitable for nano-thick silicide processing.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.126-134
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• 1996

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Korean Journal of Metals and Materials
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• v.46 no.3
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• pp.159-168
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• 2008

Thermally-evaporated 10 nm-Ni/1 nm-Ru/(30 nm or 70 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Ru-inserted nickel monosilicide. The silicide samples underwent rapid thermal anne aling at $300{\sim}1,100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution X-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope(SPM) were used to determine the cross-sectional structure and surface roughness. The silicide, which formed on single crystal silicon and 30 nm polysilicon substrate, could defer the transformation of $Ni_2Si $i and $NiSi_2 $, and was stable at temperatures up to $1,100^{\circ}C$ and $1,100^{\circ}C$, respectively. Regarding microstructure, the nano-size NiSi preferred phase was observed on single crystalline Si substrate, and agglomerate phase was shown on 30 nm-thick polycrystalline Si substrate, respectively. The silicide, formed on 70 nm polysilicon substrate, showed high resistance at temperatures >$700^{\circ}C$ caused by mixed microstructure. Through SPM analysis, we confirmed that the surface roughness increased abruptly on single crystal Si substrate while not changed on polycrystalline substrate. The Ru-inserted nickel monosilicide could maintain a low resistance in wide temperature range and is considered suitable for the nano-thick silicide process.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.248-248
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• 1999

현재 반도체 공정에서 사용하는 건식식각 공정은 고밀도 프라즈마를 사용한 플라즈마 장비를 사용하는 경향이 증대되고 있으며 이와 같은 고밀도 플라즈마 장비의 사용은 반도체 소자의 최소 선폭(CD)이 deep sub-micron으로 감소하고 반면 실리콘 웨이퍼의 크기는 8인치 직경이상으로 증가하여 가고 있어서 그 필요성이 더욱 더 증가되고 있다. 특히 TFT-LCD를 비롯한 PDP, 그리고 FED 등과 같은 여러 가지 형태의 평판 디스플레이의 제조공정에 있어서도 실리콘 기판에 비하여 대면적의 기판을 이용하고 또한 사각형 형태의 시편공정이 요구되므로 평판 디스플레이에서도 고밀도의 균일한 플라즈마 유지가 중요하다. 따라서, 본 실험에서는 여러 가지 형태의 영구자석 및 전자석의 세기 및 배열이 유도결합형 플라즈마에 미치는 효과(plasma&etch uniformity, etch rate, etc.)를 살펴보기 위해서, 유도결합형 플라즈마 chamber(210mm$\times$210mm) 내부에 magnetic cusping을 위한 영구자석용 하우스를 제작하여 표면에서 3000Gauss의 자장세기를 갖는 소형영구자석을 부착하였으며,외벽에는 chamber와 같이 사각형태로 40회 감겨진 50cm$\times$50cm 의 크기로 chamber 상하에 1개씩 Helmholtz 코일 형태로 설치하였다. 식각가스로는 Cl2, HBr, 그리고 BCl3 gas를 이용하여 axial magnet과 multidipole magnet 유무에 따른 반응성 gas의 polysilicon 식각특성을 살펴보았으며, 또한 electrostatic probe(ESP, Hiden Analytic미)를 이용하여 이들 반응성 gas에 대한 magnetically enhanced inductively coupled plasma의 특성분석을 수행하였따. Cl2, HBr, BCl3의 반응성 식각가스 조합을 이용하여 polysilicon의 식각속도 및 식각선택도를 관찰한 결과, 어떠한 자장도 가하지 않은 경우에 비해 gas의 분해율이 가장 높은 영구자석과 전자석의 조합에서 가장 높은 식각도가 관찰되었다. 특히 pure Cl2 플라즈마의 경우, Axial 방향의 전자석만을 가한 경우 식각속도에 있어서는 큰 증가를 보였으나, 식각균일도(식각균일도:8.8%)는 다소 감소하였으며, Axial 방향의 전자석과 영구자석을 조합한 경우 가장 높은 식각속도를 얻었으며, 식각균일도는 Axial 방향의 전자석만을 사용하였을 경우와 비교하여 향상되었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.594-599
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• 2005

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.23-28
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• 2004

In this paper, the properties of Mo as PMOS gate electrodes were studied. The work-function of Mo extracted from C-V characteristic curves was appropriate for PMOS. To identify the electrical and chemical stability of Mo metal gate, the changes of work-function and EOT(Effective Oxide Thickness) values were investigated after 600, 700, 800 and 90$0^{\circ}C$ RTA(Rapid Thermal Annealing). Also it was found that Mo metal gate was stable up to 90$0^{\circ}C$ with underlying SiO$_2$through X-ray diffraction measurement. Sheet resistances of Mo metal gate obtained from 4-point probe were less than 10$\Omega$/$\square$ that was much lower than those of polysilicon.