• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• THE INTERNATIONAL COMMERCE & LAW REVIEW
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• v.55
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• pp.265-290
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• 2012

CEPA (Comprehensive Economic Partnership Agreement) between India and Korea may vitalize Korean economy more and more. Currently most of Korean firms have entered into manufacturing industries like electronics and automobiles. But only a few Korean companies are trying to penetrate into Indian green industry so this paper suggest how to enter into Indian green industry, especially renewable energy sectors. First, Exporting main shaft, tower-flange and polysilicon products can be considered, as a first step of entry mode. Second, entry mode based on contract like technology licensing, strategic alliance and joint venture establishment can be also one of options. For example, Korean solar energy industry which show more competitiveness than that of Indians should try to make technological licensing on PV modules. In addition to this, they should also try to make joint ventures with right Indian partners and build up 'Solar City' nearby regions like Gurgaon in India where many Korean firms are located. Korean shipbuilding firms like Hyundai Engineering which keep on developing wind turbo engines can also try to make strategic alliance with Indian firms like Suzlon which has strong competitiveness. After that, they should explore Korean and Indian wind sector markets together. Third, brownfield investment can be last and final option as a entry mode as we consider the peculiar characteristics of renewable energy industry. Lastly, Korean government which are rush to indulge into green business should formulate more proper and realistic policies to give big incentives the concerned firms which are trying to open international green market so government should make Korean green firms not to lose good market opportunities related to green industry like renewable energy sectors. Renewable energy sectors are basically regarded as infrastructures so close contact to Indian central government as well as state government will be also required.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.823-829
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• 2004

In this paper, non-self-aligned SiGe HBTs with ${f}_\tau$ and${f}_max $above 50 GHz have been fabricated using an RPCVD(Reduced Pressure Chemical Vapor Deposition) system for wireless applications. In the proposed structure, in-situ boron doped selective epitaxial growth(BDSEG) and TiSi$_2$ were used for the base electrode to reduce base resistance and in-situ phosphorus doped polysilicon was used for the emitter electrode to reduce emitter resistance. SiGe base profiles and collector design methodology to increase ${f}_\tau$ and${f}_max $ are discussed in detail. Two SiGe HBTs with the collector-emitter breakdown voltages ${BV}_CEO$ of 3 V and 6 V were fabricated using SIC(selective ion-implanted collector) implantation. Fabricated SiGe HBTs have a current gain of 265 ∼ 285 and Early voltage of 102 ∼ 120 V, respectively. For the $1\times{8}_\mu{m}^2$ emitter, a SiGe HBT with ${BV}_CEO$= 6 V shows a cut-off frequency, ${f}_\tau$of 24.3 GHz and a maximum oscillation frequency, ${f}_max $of 47.6 GHz at $I_c$of 3.7 mA and$V_CE$ of 4 V. A SiGe HBT with ${BV}_CEO$ = 3 V shows ${f}_\tau$of 50.8 GHz and ${f}_max $ of 52.2 GHz at $I_c$ of 14.7 mA and $V_CE$ of 2 V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.52-59
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• 1989

The reliability of the thin thermal oxide was investigated by using constant current stress method. Polysilicon gate MOS capacitors with oxide thickness range of 20-25nm were used in this experiment. Automatic measurement and statistical data analysis which were essential in reliability evaluation of VLSI process preformed by HP 9000 computer. Based on TDDB results, defect density, breakdown charge (Qbd) and lifetime of oxide film were evaluated. According to the polarity of the stress, some different characteristics were shown. Defect density was 62/$cm^2$ at negative gate injection. The value of Qbd was about 30C/$cm^2$ at positive gate injection, and about 21C/$cm^2$ at negative. The current density acceleration factor was 1.43$cm^2$/A for negative gate injection, and 1.25$cm^2$/A for positive gate injection.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.34-41
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• 1984

MOEN/MO double layer which is to be used It)r the RMOS (refractory metal oxide semiconductor) gate material has been fabricated by means of low temperature reactive sputtering in N2 and Ar mixture. Good Mo2N film was obtained in the volumetric mixture of Ar:N2=95:5. The sheet resistance of the fabricated Mo7N film was about 1.20 - 1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film, and this would enable to improve the operational speed of devices fabricated with this material. When PSG (phosphorus silicate glass) was used as impurity diffusion source for the source and drain of the RMOSFET in the N2 atmosphere at about 110$0^{\circ}C$, the Mo2N was reduced to Mo resulting in much smaller sheet resistance of about 0.38 ohm/square. The threshold voltage of the RMOSFET fabricated in our experiment was - 1.5 V, and both depletion and enhancement mode RMOSFETs could be obtained.

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.267-274
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• 1997

Silicon shallow trenches applied to the STI (Shallow Trench Isolation) of integrated circuits were etched using inductively coupled $Cl_2$ and HBr/$Cl_2$ plasmas and the effects of process parameters on the etch profiles of silicon trenches and the physical damages on the trench sidewall and bottom were investigated. The increase of inductive power and bias voltage in $Cl_2$ and HBr/$Cl_2$ plasmas increased polysilicon etch rates in general, but reduced the etch selectivities over nitride. In case of $Cl_2$ plasma, low inductive power and high bias voltage showed an anisotropic trench etch profile, and also the addition of oxygen or nitrogen to chlorine increased the etch anisotropy. The use of pure HBr showed a positively angled etch profile and the addition of $Cl_2$ to HBr improved the etch profile more anisotropically. HRTEM study showed physical defects formed on the silicon trench surfaces etched in $Cl_2/N_2$ or HBr/ $Cl_2$ plasmas.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1968-1970
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• 1996

We investigate a surface-micromachined polysilicon microgyroscope, whose resonant frequencies are electrostatically-tunable after fabrication. The microgyroscope with two oscillation nudes has been designed so that the resonant frequency in the sensing mode is higher than that in the actuating mode. The microgyroscope has been fabricated by a 4-mask surface-micrormachining process, including the deep RIE of a $6{\mu}m$-thick LPCVD polycrystalline silicon layer. The resonant frequency in the sensing mode has been lowered to that in actuating mode through the adjustment of an inter-plate bias voltage; thereby achieving a frequency matching at 5.8kHz under the bias voltage of 2V in a reduced pressure of 0.1torr. For an input angular rate of $50^{\circ}/sec$, an output signal of 20mV has been measured from the tuned microgyroscope under an AC drive voltage of 2V with a DC bias voltage of 3V.

• Korean Journal of Materials Research
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• v.8 no.11
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• pp.1067-1073
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• 1998

High quality diamond films of the silicon on diamond (SOD) structure are deposited using CO and $H_2$ gas mixture in microwave plasma chemical vapor deposition (CVD), a SOD structure is fabricated using low pressure CVD polysilicon on diamond/ Si(100) substrate. The crystalline structure of the diamond films which composed of { 111} and {100} planes. were changed from octahedral one to cubo-octahedron one as the CO/$H_2$ ratios are increased. The high quality diamond films without amorphous carbon and non-diamond elements were deposited at the CO/$H_2$ flow rate of 0.18. and the main phase of the diamond films shows (111) plane. The diamond/Si(lOO) structure shows that the interface is flat without voids. The measured dielectric constant. leakage current and breakdown field were $5.31\times10^{-9}A/cm^2$ and $9\times{10^7}{\Omega}cm$ respectively.