• ETRI Journal
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• v.30 no.6
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• pp.818-825
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• 2008

This paper proposes an exponentiation method with Frobenius mappings. The main target is an exponentiation in an extension field. This idea can be applied for scalar multiplication of a rational point of an elliptic curve defined over an extension field. The proposed method is closely related to so-called interleaving exponentiation. Unlike interleaving exponentiation methods, it can carry out several exponentiations of the same base at once. This happens in some pairing-based applications. The efficiency of using Frobenius mappings for exponentiation in an extension field was well demonstrated by Avanzi and Mihailescu. Their exponentiation method efficiently decreases the number of multiplications by inversely using many Frobenius mappings. Compared to their method, although the number of multiplications needed for the proposed method increases about 20%, the number of Frobenius mappings becomes small. The proposed method is efficient for cases in which Frobenius mapping cannot be carried out quickly.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.60-68
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• 1994

In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

• Journal of the Korean Mathematical Society
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• v.42 no.2
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• pp.203-222
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• 2005

Thompson series is a Hauptmodul for a genus zero group which lies between $\Gamma$o(N) and its normalizer in PSL2(R) ([1]). We construct explicit ring class fields over an imaginary quadratic field K from the Thompson series $T_g$($\alpha$) (Theorem 4), which would be an extension of [3], Theorem 3.7.5 (2) by using the Shimura theory and the standard results of complex multiplication. Also we construct various class fields over K, over a CM-field K (${\zeta}N + {\zeta}_N^{-1}$), and over a field K (${\zeta}N$). Furthermore, we find an explicit formula for the conjugates of Tg ($\alpha$) to calculate its minimal polynomial where $\alpha$ (${\in}{\eta}$) is the quotient of a basis of an integral ideal in K.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.762-763
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• 2016

In realizing a homomorphic encryption system, the operations of encrypt, decypt, and recrypt constitute major portions. The most important common operation for each back-bone operations include a polynomial modulo multiplication for over million-bit integers, which can be obtained by performing integer Fourier transform, also known as number theoretic transform. In this paper, we adopt and modify an algorithm for calculating big integer multiplications introduced by Schonhage-Strassen to propose an efficient algorithm which can save memory. The proposed architecture of number theoretic transform has been implemented on an FPGA and evaluated.

• Journal of the Korean Mathematical Society
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• v.56 no.1
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• pp.183-195
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• 2019

Let R be a commutative ring with unity. In this paper, we characterize the unit elements, the regular elements, the ${\pi}$-regular elements and the clean elements of zero-symmetric near-ring of polynomials $R_0[x]$, when $nil(R)^2=0$. Moreover, it is shown that the set of ${\pi}$-regular elements of $R_0[x]$ forms a semigroup. These results are somewhat surprising since, in contrast to the polynomial ring case, the near-ring of polynomials has substitution for its "multiplication" operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.123-136
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• 2004

In this paper, complexity and regularity of polynomial multiplication over $GF({2^n})$ are defined by using Hamming weight of rows and columns of the matrix ever GF(2) which represents polynomial multiplication. It is shown experimentally that in order to construct the block cipher robust against differential cryptanalysis, polynomial multiplication of substitution layer and the permutation layer should have high complexity and high regularity. With result of the experiment, a way of constituting S box and G function is suggested in the block cipher whose structure is similar to SEED, which is KOREA standard of 128-bit block cipher. S box can be formed with a nonlinear function and an affine transform. Nonlinear function must be strong with differential attack and linear attack, and it consists of an inverse number over $GF({2^8})$ which has neither a fixed pout, whose input and output are the same except 0 and 1, nor an opposite fixed number, whose output is one`s complement of the input. Affine transform can be constituted so that the input/output correlation can be the lowest and there can be no fixed point or opposite fixed point. G function undergoes linear transform with 4 S-box outputs using the matrix of 4${\times}$4 over $GF({2^8})$. The components in the matrix of linear transformation have high complexity and high regularity. Furthermore, G function can be constituted so that MDS(Maximum Distance Separable) code can be formed, SAC(Strict Avalanche Criterion) can be met, and there can be no weak input where a fixed point an opposite fixed point, and output can be two`s complement of input. The primitive polynomials of nonlinear function affine transform and linear transformation are different each other. The S box and G function suggested in this paper can be used as a constituent of the block cipher with high security, in that they are strong with differential attack and linear attack with no weak input and they are excellent at diffusion.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.27-34
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• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.