A Design of Multiplier Over $GF(2^m)$ using the Irreducible Trinomial

$GF(2^m)$의 기약 3 항식을 이용한 승산기 설계

  • 황종학 (인하대학교 전자공학과) ;
  • 심재환 (인하대학교 전자공학과) ;
  • 최재석 (인덕대학 메카트로닉스과) ;
  • 김흥수 (인하대학교 전자공학과)
  • Published : 2001.02.28

Abstract

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

[ $GF(2^m)$ ]의 기약 3항식인 $x^m+x+1$을 이용한 승산기 알고리즘은 Mastrovito에 의해 제안되었다. 본 논문에서는 기약 3항식 $x^m+x+1$에서 1$GF(2^m)$상의 원시 기약 3 항식을 전개하여 회로를 간략화 하였으며, 제안된 승산기 설계는 규칙적이며 모듈러 구조, 그리고 간단한 제어신호를 요하기 때문에 VLSI 실현이 용이하다고 사료된다.

Keywords

References

  1. H.M. Shao, T.K.Truong, L.J. Deutsch, J,H. Yaeh and I.S. Reed, 'A VLSI design of a pipeling reed-solomon decoder,' IEEE Trans. Comput., vol. C 34, pp. 393-403, May 1985
  2. C.S. Yeh, I.S Reed and T.K. Truong, 'Systolic multipliers for finite field GF($2^m$),' IEEE Trans. Comput., vol. C-33, pp. 357-360, Apr. 1984
  3. C.C. Wang, T.K. Truong, H.M. Shao, L.J. Deutsch, J.K. Omura and I.S. Reed, 'VLSI architecture for computing multiplications and inverses in GF($2^m$,),' IEEE Trans. Comput., vol. C-34, pp. 709-717, Aug. 1985
  4. K.C Smith. 'The prospect for multivalued logic : A technology and applications view.' IEEE Trans. Comput., vol. C-30, pp. 619-634, Sept. 1981
  5. S.L. Hurst, 'Multiple-valued logic-its future,' IEEE Trans. Comput., vol. C-33, pp. 1161-1179, Dec. 1984
  6. J.T. Butler, 'Multiple-valued logic in VLSI,' IEEE Computer Soc. Press, 1991
  7. H. K. Seong and H.S. Kim, 'A construction of celluar array multiplier over GF($2^m$),' KITE, vol. 26, no. 4, pp. 81-87. April 1989
  8. P. A. Scott, S.E. Tarvares and L.E. Peppard, 'A fast multiplier for GF($2^m$),' IEEE J. Select. Areas Commun., vol. SAC-4, Jan. 1986
  9. S. Bandyopadhyay and A. Sengupta, 'Algorithms for multiplication in Galois field for implementation using systolic arrays,' lEE Proc., vol. 135. PT. E. no. 6, pp. 336-339, Nov. 1988
  10. C.L. Wang and J.L. Lin, 'Systolic array implementation of multipliers for finite fields GF($2^m$),' IEEE Trans. Circuits and Systems, vol. 38, no. 7, July 1991 https://doi.org/10.1109/31.135751
  11. J. T. Butler and H. G. Kerkhoff, 'Multiple-valued CCD circuits,' IEEE Comput., pp. 58-67. Apr. 1988 https://doi.org/10.1109/2.51
  12. M.H. Abd-El-Barr and Z. G. Vranesic, 'Cost reduction in the CCD Realization of MVMT functions,' IEEE Trans. Comput., vol. C-39, no. 5, May 1990 https://doi.org/10.1109/12.53584
  13. Kiamal Z. Pekmestzi, 'Multiplexer-Based Array Multipliers,' IEEE Trans. Compt., vol. 48, no. 1, pp. 15-23, Jan. 1999 https://doi.org/10.1109/12.743408
  14. H.K. Seong and K.S. Yoon, 'A Study on Implementation of Multiple-Valued Arithmetic Processer using Current Mode CMOS,' KITE, vol. 36, no. C-4, pp. 35-45. Aug. 1999
  15. C.K. Koc and B. Sunar, 'Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields,' IEEE Trans. Comput., vol. c-47, no. 3, pp. 353-356, March 1998 https://doi.org/10.1109/12.660172
  16. C. Paar, P. Felischmann, and P. Roelse, 'Efficient multiplier architectures for Galois fields GF$2^m$),' IEEE Trans. Comput., vol. C-47, no. 2, pp. 162-170, Feb. 1998 https://doi.org/10.1109/12.663762
  17. J.H. Hwang, S.Y. Park, B.S. Shin, and H.S. Kim, 'Multiplexer-Based Array Multipliers over GF($2^m$),' KITE, vol. 37, no. SC-4, pp. 35-41. July 2000
  18. B. Sunar and C.K. Koc, 'Mastrovito Multiplier for All Trinomials,' IEEE Trans. Comput., vol. c-48, no. 5, pp. 522-527, May 1999 https://doi.org/10.1109/12.769434
  19. E. D. Mastrovito, 'VLSI Architectures for Multiplication Over Finite Field GF($2^m$),' Applied Algebraic Algorithms, and Error Correcting Code, Proc. Sixth Int'l Conf., AAECC-6, T.Mora,ed., pp. 297-309, Rome, July I988
  20. E.D. Mastrovito, 'VLSI Architectures for Computation in Galois Fields,' PhD thesis, Linkoping Univ., Dept. of Electrical Eng., Linkoping, Sweden, 1991