• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.664-667
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• 1997

For higher component density per chip, it is necessary to identify and control the semiconductor manufacturing process more stringently. Recently, neural networks have been identified as one of the most promising techniques for modeling and control of complicated processes such as plasma etching process. Since wafer states after each run using identical recipe may differ from each other, conventional neural network models utilizing input factors only cannot represent the actual state of process and equipment. In this paper, in addition to the input factors of the recipe, real-time tool data are utilized for modeling of 64M DRAM s-poly plasma etching process to reflect the actual state of process and equipment. For real-time tool data, we collect optical emission spectroscopy (OES) data. Through principal component analysis (PCA), we extract principal components from entire OES data. And then these principal components are included to input parameters of neural network model. Finally neural network model is trained using feed forward error back propagation (FFEBP) algorithm. As a results, simulation results exhibit good wafer state prediction capability after plasma etching process.

• International Journal of Control, Automation, and Systems
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• v.6 no.3
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• pp.386-393
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• 2008

A position control method for interpolating aspherical grinding and polishing tool path was reviewed and experimented in a nano precision machine. The position-base algorithm was reformed from the time-base algorithm, proposed in the previous study. The characteristics of the algorithm were in the velocity control loop with position feedback. The aspherical surface was divided by an interval at which each velocity and acceleration were calculated. The theoretical velocity was corrected by position error during processing. In the experiment, a machine was constructed and nano-scale linear encoders were installed at each axis. Relation between process parameters and the variation of position error was monitored and discussed. The best result from optimized parameters showed that the accuracy was 150nm and improved from the previous report.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.387-396
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• 2003

This paper provides an approximation algorithm for STP-MSP(Steiner Tree Problem with minimum number of Steiner Points).Because it seems to be impossible to have a PTAS(Polynomial Time Approximation Schemes), which gives the near optimal solutions, for the problem, the algorithm of this paper is an alternative that has the approximation ratio 2 with $n^{O(1)}$ run time. The importance of this paper is the potential to solve other related unsolved problems. The idea of this paper is to distribute the error allowance over the problem instance so that we may reduce the run time to polynomial bound out of infinitely many cases. There are earlier works[1,2] that show the approximations that have practical run times with the ratio of bigger than 2, but this paper shows the existence of a poly time approximation algorithm with the ratio 2.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.13-19
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• 1998

The Median of a set of number is a number which partitions the given set. The specified numbers of a set partitions in one subset and in another subset. In Image Processing, The Sorting method of numbers of one subset equal to the previous Median Filtering. but The Sorting method of numbers of another subset not equal to in the other. In this paper, a fast two-dimentional Median Filtering Algorithm is proposed. The Algorithm designed in such a during the partitioning of the previous window are used. Test results obtained by running the Algorithm on IBM PC(586) are presented and its filtering. It is shown that the proposed Algorithm's processing time is faster and independent of the number of bits used to represent the data values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.119-126
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• 2019

The partial inverse optimization problem is an interesting variant of the inverse optimization problem in which the given instance of an optimization problem need to be modified so that a prescribed partial solution can constitute a part of an optimal solution in the modified instance. In this paper, we consider the traveling salesman problem defined on the line (TSP on the line) which has many applications such as item delivery systems, the collection of objects from storage shelves, and so on. It is worth studying the partial inverse TSP on the line, defined as follows. We are given n requests on the line, and a sequence of k requests that need to be served consecutively. Each request has a specific position on the real line and should be served by the server traveling on the line. The task is to modify as little as possible the position vector associated with n requests so that the prescribed sequence can constitute a part of the optimal solution (minimum Hamiltonian cycle) of TSP on the line. In this paper, we show that the partial inverse TSP on the line and its variant can be solved in polynomial time when the sever is equiped with a specific internal algorithm Forward Trip or with a general optimal algorithm.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• The Bulletin of The Korean Astronomical Society
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• v.41 no.2
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• pp.61.1-61.1
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• 2016

Black hole (BH) mass is a fundamental quantity to understand BH growth, galaxy evolution, and connection between them. Thus, obtaining accurate and precise BH mass estimates over cosmic time is of paramount importance. The rest-frame UV CIV ${\lambda}1549$ broad emission line is commonly used for BH mass estimates in high-redshift AGNs (i.e., $2{\leq}z{\leq}5$) when single-epoch (SE) optical spectra are available. Achieving correct and accurate calibration for CIV-based SE BH mass estimators against the most reliable reverberation-mapping based BH mass estimates is thus practically important and still useful. By performing multi-component spectral decomposition analysis to obtained high-quality HST UV spectra for the updated sample of local reverberation-mapped AGNs including new HST STIS observations, CIV emission line widths and continuum luminosities are consistently measured. Using a Bayesian hierarchical model with MCMC sampling based on Hamiltonian Monte Carlo algorithm (Stan NUTS), we provide the most consistent and accurate calibration of CIV-based BH mass estimators for the three line width characterizations, i.e., full width at half maximum (FWHM), line dispersion (${\sigma}_{line}$), and mean absolute deviation (MAD), in the extended BH mass dynamic range of log $M_{BH}/M_{\odot}=6.5-9.1$.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.