• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.373-373
• /
• 2012

염료 감응형 태양전지는 기존 Si 기반 PN접합 무기 태양전지에 비해서 경제적이다. 하지만 그 에너지 변환 효율은 아직까지 세계 최고 수준이 10%밖에 도달하지 못하였다. 그래서 다양한 방식의 효율개선 연구가 활발히 진행되고 있는 실정이다. 본 연구에서는 진공원자층증착(ALD)를 이용하여 Core-shell 구조의 $TiO_2$층 위에 아주 얇고 균일한 $Al_2O_3$ (알루미나) 산화막을 입혔다. 이를 통해서 염료감응형 태양전지의 에너지 변환 효율을 향상시켰다. 본 연구에서는 진공원자층증착(ALD)기술을 이용한 $Al_2O_3$ (알루미나) 산화막의 증착조건에 따른 염료감응태양전지의 효율 개선 매커니즘에 대해서 고찰하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.565-568
• /
• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

• Proceedings of the KIEE Conference
• /
• 2009.04b
• /
• pp.248-250
• /
• 2009

고효율 태양전지를 위한 결정질 태양전지의 구조 중 UNSW에서 개발한 BCSC(buried contact solar cell)가 있는데, 이는 전면 전극을 laser 처리 후 무전해 니켈 도금으로 형성한 것이다. 이같은 전면 전극을 형성하기 위해서는 무전해 nickel 도금 후 열처리가 필수적이다. 우리는 이 공정을 확립하기 위해 결정질 wafer에 후면을 PECVD로 SiNx막을 형성하여 $30\Omega/\square$로 도핑한 후 후면을 불산으로 제거한 상태에서 양면을 니켈 무전해 도금으로 전극을 형성하여 $300^{\circ}C,\;350^{\circ}C,\;400^{\circ}C$에서 각각 3,6,9분간 진행하였다. 그 결과 $400^{\circ}C$에서 3분간 열처리된 sample이 상대적으로 가장 명확한 IV curve를 형성하였다. 이 실험의 결과는 PN 접합 구조에서 전극을 nickel로 사용할 때 유용하게 사용될 수 있다.

• Journal of the Korean Society of Radiology
• /
• v.3 no.1
• /
• pp.11-15
• /
• 2009

In this study, the basic research verifying possibility of applications as radiology image sensor in Digital Radiography was performed, the radiology image sensor was fabricated using a multi-layer technique to decrease dark current. High efficiency materials in substitution for Amorphous Selenium(a-Se) have been studied as a direct method of imaging detector in Digital Radiography to decrease dark current by using PN junction or Hetero junction already used as solar cell, semiconductor. Particle-In -Binder method is used to fabricate radiology image sensor because it has a lot of advantages such as fabrication convenient, high yield, suitability for large area sensor. But high leakage current is one of main problem in Particle-In -Binder method. To make up for the weak points, multi-layer technique is used, and it is considered that high efficient digital radiation sensor can be fabricated with easy and convenient process. In this study, electrical properties such as leakage current, sensitivity, signal linearity is measured to evaluate multi-layer radiation sensor material.

• Radiation Oncology Journal
• /
• v.7 no.1
• /
• pp.93-100
• /
• 1989

Several combinations of measuring devices and phantoms were studied to measure electron beams. Silicon Pmt junction diode was used to find the dependence of depth dose profile on field size on axis of electron beam Depths of 50, 80 and $90\%$ doses increased with the field size for small fields. For some larger fields, they were nearly constant. The smallest of field sizes over which the parameters were constant was enlarged with increase of the energy of electron beams. Depth dose distributions on axis of electron beam of $10\times10cm^2$ field were studied with several combinations of measuring devices and phantoms. Cylindrical ion chamber could not be used for measurement of surface dose, and was not convenient for measurement of near surface region of 6MeV electron. With some exceptions, parameters agreed well with those studied by different devices and phantoms. Surface dose in some energies showed $4\%$ difference between maximum and minimum. For 18MeV, depths of 80 and $90\%$ doses were considerably shallower by film than by others. Parallel-plate ion chamber with polystyrene phamtom and silicon PN junction would be recommended for measurement of central axis depth dose of electron beams with considerably large field size. It is desirable not to use cylindrical ion chamber for the purpose of measurement of surface dose or near surface region for lower energy electron beam. It is questionable that film would be recommended for measurement of dose distribution of electron with high energy like as 18MeV.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.64-71
• /
• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.12
• /
• pp.2366-2373
• /
• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.4
• /
• pp.413-417
• /
• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.2
• /
• pp.89-95
• /
• 1995

The structure of boron ion-implanted pn junctio in the vacancy-doped p-type HgCdTe was investigated with the differential Hall measurement. The as-implanted junction showed the electron concentration as high as 1${\times}10^{18}/cm^{3}$ and the junction depth of 0.6.mu.m. When the HgCdTe junction was heated in oven, the electron concentration near the junction decreased and the junction depth increased as the annealing temperature and time increased. The junction structure after the thermal annealing was n$^{+}$/n$^{-}$/p. For the 200.deg. C 20min annealed sample, the electron mobility was 10$^{4}cm^{2}/V{\cdot}$s near the surface(n$^{+}$), and was larger thatn 10$^{5}cm^{2}/V{\cdot}$s near the junction(n$^{+}$). The junction formation mechanism is conjectured as follows. When HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms near the surface. The displaced Hg vacancies diffuse in easily by the thernal treatment and a fill the Hg vacancies in the p-HgCdTe substrate. With the Hg vacancies filled completely, the GfCdTe substrate becomes n-type because of the residual n-type impurity which was added during the wafer growing. Therefore, the n$^{+}$/n$^{-}$/p regions are formed by crystal defects, residual impurities, and Hg vacancies, respectively.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.406-406
• /
• 2011

결정질 태양전지에서 도핑(Doping)은 반도체(Semiconductor)의 PN 접합(Junction)을 형성하는 중요한 역할을 한다. 도핑은 반도체에 불순물(Dopant)을 주입하는 공정으로 고온에서 진행되며 온도는 중요한 변수(Parameter)로 작용한다. 본 연구에서는 여러 가지 에미터(emitter)층 형성방법 중에 가장 저가이면서 공정과정이 간단하며 대면적 도핑이 용의한 Spray 방법을 통해 효과적인 에미터 층 형성의 최적화를 위해 DI water에 각각 1%, 3%, 5% 7%로 희석된 H3PO4용액 으로 850$^{\circ}C$에서 열처리 시간을 가변해 가며 최적화된 면저항과 표면농도 특성을 분석하였다. 도핑소스가 웨이퍼(wafer) 각각의 표면에 흡착시킨 후 오븐에 넣어 150$^{\circ}C$에서 5분간 건조시킨 후 퍼니스(furance)에 넣어 시간을 가변해 가며 도핑시켰다. Spray 방식은 기존의 방식보다 저렴하고 In-line 공정에 적합하며 대용량으로 전환이 쉽다는 많은 장점을 가지고 있다. 도핑시 먼저 spray를 이용하여 웨이퍼 표면에 균일하게 용액을 흡착시킨 후 오븐에서 150$^{\circ}C$에서 5분간 건조 후 furnace에 넣어 850$^{\circ}C$에서 시간을 가변 해가며 실험하였다. H3PO4용액의 비율이 1%일 때는 2분 이상 열처리를 하였을 때 60${\Omega}/{\Box}$ 이하로 내려가지 않았다. 이는 최초 표면농도가 낮아 더 이상 확산되지 않음을 의미한다. 또한 H3PO4의 비율이 3% 이상일 때는 열처리 시간이 1분 이하일 때 면저항의 변화가 거의 없었으나 2분 이상일 때는 시간에 따라서 점차 낮아졌으며 균일도 역시 좋아졌다. 이는 H3PO4의 비율이 3% 이상일 때는 표면농도가 높아서 1분 이하의 열처리 시간에서는 확산해 들어가는 양이 거의 같음을 알 수 있었다.