• 한국통신학회논문지
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• 제28권11C호
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• pp.1152-1160
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• 2003

본 논문에서는 다양한 해상도의 신호 입력을 지원하는 고품위급 모니터의 디지털 신호처리 회로를 제안한다. 기존의 디지털 회로에서 ADC(Analog to Digital Convertor)와 VDP(Video Display Processor)로부터 발생하는 내부 디지털 PLL(Phase-locked Loop)의 낮은 성능과 IC의 내부 편차문제, 모듈간의 상이한 전압 차이 때문에, 다양한 입력 신호에서 안정된 동기신호 처리를 할 수 없는 문제가 있었다. 이를 해결하기 위해서 다양한 해상도의 신호 입력으로부터 동기 신호들의 규칙성을 이용하여 동기 신호를 관리하면서 시스템의 간섭을 최소화하는 동기신호 최적화 기법을 제안하였다. 제안한 방법을 적용한 결과 다양한 해상도에서 안정적으로 동기신호를 처리함으로써 여러 모드의 입력신호에 대응할 수 있었다.

• 한국군사과학기술학회지
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• 제14권6호
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• pp.1043-1048
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• 2011

In this paper, a newsynchronization technique applied to burst-mode communication is proposed. A synchronization technique is to estimate carrier frequency and phase offsets in a noisy channel environment. A fundamental problem for estimating the parameters(carrier phase and frequency offsets) in burst-mode transmission is that the ways of pursuing estimation accuracy and transmission efficiency are always trade-off. To solve this problem, a new carrier recovery technique is proposed to improve the transmission efficiency with reliable performance especially at low S/N. In the proposed technique, the synchronization parameters are first estimated based on a data-aided feed-forward estimation scheme. Then, a phase tracker using decision-directed DPLL estimates the phase offset for the data portion of the burst data. From simulation results, it shows fast synchronization with shorter preamble maintaining reasonable BER performance at low S/N.

• 한국음향학회지
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• 제41권2호
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• pp.159-165
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• 2022

본 논문에서는 수중 음향통신에서 Binary Phase Shift Keying(BPSK) 변조방식에 대한 프레임 동기 구조를 제안하였다. 제안된 프레임 동기 구조는 크게 두 가지로 나뉜다. 우선, 비동기 방식 상관과 Sliding 고속 푸리에 변환 방식으로 프레임의 대략적인 위치와 주파수 옵셋을 획득한다. 두번째는 주파수 오차를 신호에 보상한 후, 동기 방식 상관으로 정확한 프레임의 위치를 확인한다. 프레임 동기 구조의 성능 확인을 위해 해상실험을 수행하였다. 수신신호는 채널 특성으로 인해 전력이 크게 감소함을 확인하였으며, 이를 통해 비동기 방식 상관과 Sliding 고속 푸리에 변환 방식의 한계를 확인하였다. 결과적으로, 주파수 오차를 보상한 후 동기 방식 상관방식을 사용함으로써 안정적인 프레임 동기를 획득할 수 있었다.

• 디지털산업정보학회논문지
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• 제9권4호
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• pp.51-57
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• 2013

Research on calibration of array antenna has become a hot spot in the area of signal processing and it is necessary to obtain the phase mismatch of each antenna channel. This paper presents a new calibration method for an array antenna system. In order to calibrate the phase mismatch of each antenna channel, we used primary synchronization signal (PSS) which exists in LTE downlink frame. Primary synchronization signal (PSS) is based on a Zadoff-Chu sequence which has a good correlation characteristic. By using correlation calculation, we can extract primary synchronization signal (PSS). After extracting primary synchronization signal (PSS), we use it to calibrate and reduce the phase errors of each antenna channel. In order to verify the new array antenna calibration algorithm which is proposed in this paper, we have simulated the proposed algorithm by using MATLAB. The array antenna system consists of two antenna elements. The phase mismatch of first antenna and second antenna is calculated accurately by proposed algorithm in the experiment test. Theory analysis and MATLAB simulation results are shown to verify the calibration algorithm.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 춘계학술발표회 논문집
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• pp.160-163
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• 1986

In a digital telecommunication network, the clock synchronization is inevitable to prevent the data loss caused by inconsistency of clock frequencies. This paper descries the considerations necessary for synchronization and the implementation of the clock synchronization system using digital processing phase locked loop method in TDX-1 switching system.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.315-317
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• 2003

Neural oscillator is applied in oscillatory systems (Analysis of image information, Voice recognition. Etc...). If we apply established EBPA(Error back Propagation Algorithm) to oscillatory system, we are difficult to presume complicated input's patterns. Therefore, it requires more data at training, and approximation of convergent speed is difficult. In this paper, I studied the neural oscillator as synchronized states with appropriate phase relation between neurons and recognized the Korean alphabet using Neural Oscillator Phase model Synchronization.

• Journal of Power Electronics
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• 제16권5호
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• pp.1939-1949
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• 2016

This paper presents an alternative frequency adaptive grid synchronization technique named HDN-FLL, which can accurately extract the fundamental positive- and negative-sequence components and interested harmonics in adverse three-phase grid voltage. The HDN-FLL is based on the harmonic decoupling network (HDN) consisting of multiple first order complex vector filters (FOCVF) with a frequency-locked loop (FLL), which makes the system frequency adaptive. The stability of the proposed FLL is strictly verified to be global asymptotically stable. In addition, the linearization and parameters tuning of the FLL is also discussed. The structure of the HDN has been widely used as a prefilter in grid synchronization techniques. However, the stability of the general HDN is seldom discussed. In this paper, the transfer function expression of the general HDN is deduced and its stability is verified by the root locus method. To show the advantages of the HDN-FLL, a simulation comparison with other gird synchronization methods is carried out. Experimental results verify the excellent performance of the proposed synchronization method.

• 한국멀티미디어학회논문지
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• 제18권4호
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• pp.452-459
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• 2015

Three synchronization issues, i.e., phase, frequency, and symbol time, have to be properly controlled to achieve distributed beamforming gain. In this paper, the impacts of synchronization errors in distributed beamforming are analyzed for both single-carrier and OFDM systems. When the channel is constant over a symbol duration, the performance degradation due to phase offset is the same for both single-carrier and OFDM systems. For symbol timing offset in OFDM systems, high frequency subcarriers are more susceptible as compared to low frequency ones. Frequency offset is critical in OFDM systems since it leads to interference from the other subcarriers as well as power loss in the desired signal.

• 제어로봇시스템학회논문지
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• 제14권7호
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• pp.624-628
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• 2008

This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

• 한국통신학회논문지
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• 제19권5호
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• pp.787-795
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• 1994

본 논문에서는 랜덤한 NRZ 신호에 동기된 클럭을 추출하는 비트 동기 알고리즘을 제안하고 회로 설계 및 성능을 분석하였다. 설계된 동기 회로는 데이터 천이 검출기, Mod 64 계수기, 위상비교 및 제어기, 64분주기로 구성되었으며, 데이터 처리 속도가 16Kbps로서 마스터 클럭은 4.096MHz, 그리고 위상 보정은 매 비트마다 데이터 신호 주기의 1/64만큼 이루어진다. 입력신호에 대한 위상 지터의 최대 허용치는 23.8%이고, 복원된 클럭의 편차가 1.6%임을 실험을 통해 측정하였다. 동기 회로는 완전 디지틀 회로로서 하나의 반도체 칩으로 실현이 용이할 뿐 아니라 저속의 디지틀 이동통신에 효과적이다.