• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1101-1107
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• 2017

In this paper, a robust and fast grid synchronization method of a three-phase power converter is proposed. The amplitude and phase information of grid voltages are essential for power converters to be properly connected into the utility. The phase-lock-loop in synchronous reference frame has been widely adopted for the three-phase converter system since it shows a satisfactory performance under balanced grid voltages. However, power converters often operate under abnormal grid conditions, i.e. unbalanced by grid faults and frequency variations, and thus a proper active and reactive power control cannot be guaranteed. The proposed method adopts a second order generalized integrator in synchronous reference frame to detect positive sequence components under unbalanced grid voltages. The proposed method has a fast and robust performance due to its higher gain and frequency adaptive capability. Simulation and experimental results show the verification of the proposed synchronization algorithm and the effectiveness to detect positive sequence voltage.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.652-660
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• 2000

This paper proposes a new type of sampling Phase Detector (SPD) for NRZ random bit synchronization circuit. The proposed SPD calculates the mean value of phase difference between bit interval of input signal and period of local reference. Simulated and experimental results show that the proposed SPD is applicable to the phase detector for NRZ random signal. finally the Random NRZ bit synchronization circuit. is designed and implemented by using SPD.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.581-584
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• 2003

It is important to know phase offsets of PN (Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to make a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration far an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time of the proposed synchronization method is derived analytically, and we see that the method acquires very fast acquisition in the high SNR (Signal-to- Noise Ratio) environment.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.285-290
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• 2020

This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.2
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• pp.347-353
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• 2004

Neural oscillator can be applied to oscillator systems such as analysis of image information, voice recognition and etc, Conventional learning algorithms(Neural Network or EBPA(Error Back Propagation Algorithm)) are not proper for oscillatory systems with the complicate input patterns because of its too much complex structure. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase locked loop) function and a simple Hebbian learning rule, Therefore, in this paper, it will introduce an technique for Recognition of the Korean Character using Phase Synchronization Neural Oscillator and will show the result of simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.701-704
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• 2004

In this paper, we proposed that the synchronization method for build small world. In order to build a small world, we used Chua's oscillator which well represent the chaos dynamics and composed several stage with Chua's oscillator by using coupled synchronization method. This paper shows a synchronization result in the small world network using coupled synchronization method. Not only time series and phase plane are implemented but also degree of synchronization in the small world network is presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1700-1705
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• 2013

A second harmonic millimeter wave oscillator utilizing sub-harmonic injection-synchronization is presented. A 8.7GHz oscillator with MES-FET is designed, and is driven as a harmonic output oscillator at 17.4GHz by means of sub-harmonic injection-synchronization. The oscillator operates as a multiplier as well as a oscillator in this scheme. Adopting this method, a high sable, high frequency millimeter wave source is obtainable even though self-oscillating frequency of an oscillator is relatively low. The range of injection-synchronization is about 26MHz, and is proportional to the input sub-harmonic power. The spectrum analysis of the 2nd harmonic output frequency shows remarkably decreased the phase noise level.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.6
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• pp.819-827
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• 2013

Compared to legacy frequency hopping communications, future radio communications are required the secure and high data rate, ad-hoc network communication. In this paper, we have designed the network communication structure on the frequency hopping mode, and analyzed the performance of synchronization on the frequency hopping network radio systems. The design results are shown the initial sync. phase of approximately 9 hops and the traffic packet phase of approximately 30 hops. Also, we have simulated the performance on the communication conditions which are carrier bandwidth of 50kHz, user data rate of 64kbps and OQPSK modulation scheme in AWGN. In the simulation, we analyzed the correlation and the performance of synchronization success. The result of simulation show 99% probability for synchronization success at $E_b/N_o$ -4dB.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.441-447
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• 2022

In this paper, we propose a FLL-assisted-PLL based time synchronization algorithm for telemetry systems where frequency and phase errors exist in time synchronization pulse. The telemetry system may analyze the flight state by acquiring the state information in the distributed system. Therefor, in order to collect each state information without errors, precise time synchronization between the master and the slave is required. At this time, the master's time pulse have frequency and phase changes that can be caused by external and internal factors, so a method to maintain precision time synchronization is essential to provide telemetry data continuously. We propose the FLL-assisted-PLL based algorithm that is capable of high-speed synchronization and has high time synchronization accuracy. The proposed algorithm is verified through python simulation, and the VHDL Logic has been implemented in FPGA to check the performance according to the frequency errors and phase errors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.481-487
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• 2013

To successfully accomplish a bit synchronization, a synchronizer should exploit a preamble pattern. A MFM (modified frequency modulation) flag is uses as a preamble in a PJM (phase jitter modulation) mode RFID standard. In the recent work, a synchronizer for a PJM mode tag was proposed, which is composed of several correlators. In this paper, we present a new bit synchronizer in which a coarse synchronization is done as in the previous work while a fine synchronization is performed via exploiting a violation bit included in the MFM flag. We show that the proposed synchronizer can significantly reduce the overall hardware complexity at the expense of slight burden to a demodulator structure. Through simulation, we also show that its performance is comparable to that of the previous system despite its hardware simplicity.