• 한국정보통신설비학회:학술대회논문집
• /
• 2007.08a
• /
• pp.436-439
• /
• 2007

This paper describes the optimization of PGS(Patterned Ground Shield) of 5.5 turns rectangular spiral inductor using Taguchi's method. PGS is decrease method of parasite component by silicon substrate among dielectric loss reduction method. By using the taguchi's method, each parameter is fixed upon that PGS high poison(A), slot spacing(B), strip width(C) and overlap turn number(D) of PGS design parameter. Then we verified that percentage contribution and design sensitivity analysis of each parameter and level by signal to noise ratio of larger-the-better type. We consider percentage contribution and design sensitivity of each parameter and level, and then verify that model of optimization for PGS is lower inductance decreasing ratio and higher Q-factor increasing ratio by EM simulation.

• 한국정보통신설비학회:학술대회논문집
• /
• 2006.08a
• /
• pp.153-157
• /
• 2006

본 논문에서는 SoC 공정에 적용 가능한 spiral 인덕터의 특성에 대해 다루었다. 일정한 크기의 인덕터에서 턴 수의 변화에 따른 인덕턴스와 Q-factor의 변화를 보았다. HFSS 프로그램을 사용하여 턴 수와 선로의 폭이 같은 조건하에서 사각형 구조와 팔각형 구조를 갖는 인덕터의 인덕턴스와 Q-factor의 ?냅? 계산하였다. 사각형 구조와 팔각형 구조 모두 선로 폭 보다는 턴 수가 증가할수록 인덕턴스가 증가하였다. 턴 수가 증가할수록 Q-factor의 값은 사각형 구조는 감소한 반면 팔각형 구조는 증가하였다. spiral과 실리콘 사이에 PGS(Patterned Ground Shield)를 삽입하여 인덕턴스 및 Q-factor의 변화를 비교 분석하였다. 그 결과 PGS의 사용으로 사각형 구조와 팔각형 구조에서 턴 수에 따라 Q-factor의 값이 구조에 따라 서로 다른 방향으로 증감하는 것을 확인할 수 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.11
• /
• pp.1967-1971
• /
• 2007

In this paper, we verified basic forms and equivalent circuits of spiral inductors and various kinds of parasitics of equivalent circuits by using HFSS and Nexxim program that were 3-D EM analysis tools, and fabrication on-chip spiral inductors using Hynix's 0.25um 1-poly and 5-metal CMOS process. Comparing with PGS(patterned ground shield) and NPGS(non patterned ground shield) of spiral inductors of 3.5 turn, 4.5 turn and 5.5 turn, etc, the application of PGS could improve maximum Q value by 8-12%.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.35-38
• /
• 2008

In this paper, study noise performance of LNA to enhance Q-factor of input circuit by patterned ground shield is inserted inductor using TSMC 0.18um. Applied LNA technology is cascode method. The input matching circuit was constituted on-chip and wirebonding inductor. Taguchi's method is used for the best suited structure of PGS. We confirmed enhancement of Q-factor by inserted PGS into inductor. The input matching circuit enhanced Q-factor by inductor with PGS improve noise figure of LNA.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.272-273
• /
• 2007

This paper presents the characteristic of rectangular and octagonal spiral inductor using PGS(Patterned Ground Shield). We investigated variation of inductance and Q-factor with changing of turn number at fixed width, spacing and inner diameter. We confirmed that characteristic of inductance and Q-factor be appled PGS in rectangular and octagonal types spiral inductor by EM simulation tool. Inductance decreased irrespective of structure but Q-factor increased. When PGS not exist, Q-factor of Inductor is analogous at classification frequency but, rectangular is a few larger then octagonal in small turn number. The other side, When PGS is inserted, we confirmed that octagonal lager then rectangular in many turn number. Q-factor is improved in case of octagonal structure and small turn number by PGS effect.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.50-56
• /
• 2000

The integrated circuit interconnection lines are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can significantly reduce the power loss through the interconnect lines over wide frequency ranges as the PGS shields the lossy silicon substrate. The transmission line characteristics of the PGS interconnect lines are analyzed and identified that the PGS reduces the wave length of the interconnect line.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.5 s.120
• /
• pp.530-538
• /
• 2007

An inductor library for efficient low cost RFIC design has been developed based on a standard digital 0.18 ${\mu}m$ CMOS process. The developed library provides four structural variations that are most popular in RFIC design; standard spiral structure, patterned ground shield(PGS) structure to enhance quality factor, stacked structure to enable high inductance values in a given silicon area, multilayer structure to lower series resistance. Electromagnetic simulation, equivalent circuit, and parameter extraction processes have been verified based on measurement results. The extensive measurement and simulation results of the inductor library can be a great asset for low cost RFIC design and development.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.2
• /
• pp.363-368
• /
• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• Proceedings of the KIEE Conference
• /
• 2008.10a
• /
• pp.107-108
• /
• 2008

This article describes optimization for PGS(Patterned Ground Shield) of rectangular spiral inductor using Taguchi's Design of Experiment. PGS is decrease method of parasite component by silicon substrate among dielectric loss reduction method. Using taguchi's design of experiment, each parameter is fixed upon that PGS high poison(A), slot spacing(B), strip width(C) and overlap turn number(D) of PGS design parameter. Then we verified that percentage contribution and design sensitivity analysis of each parameter and level by signal to noise ratio of larger-the-better type. We consider percentage contribution and design sensitivity of each parameter and level, and then verify that model of optimization for PGS is lower inductance decreasing ratio and higher Q-factor increasing ratio by EM simulation.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.1399-1400
• /
• 2008

본 논문에서는 TSMC 0.18um 공정을 이용하여 2.45GHz 대역에서 동작하는 RFID 리더에 적용 할 수 있는 전압제어 발진기를 설계하였다. 위상 잡음 특성 향상을 위해 PMOS, NMOS 소자를 대칭으로 구성한 complementary cross-coupled LC 발진기 구조로 설계 하였고 MOS 배렉터를 이용하여 주파수를 가변 하였다. 또한 공정에서 사용되는 인덕터에 차폐 도체면(PGS:Patterned Ground Shield) 구조를 삽입했을 때 인덕터의 품질계수가 약 5.82% 향상되었고. 이에 따른 위상 잡음은 1MHz offset 주파수에서 PGS를 삽입하지 않는 구조에서는 -102.666dBc/Hz 이며, PGS 구조를 삽입한 구조는 -104.328dBc/Hz로 약1.662dBc 정도의 성능이 향상 되었다. 전압제어 발진기 Core 사이즈는 900um ${\times}$ 590um이고 주파수 가변 범위는 배렉터 전압 1.2${\sim}$2.1V에서 249MHz로 11.4% 특성을 보였다. 1.8V공급전압에서 5.76mW의 전력소모를 보였다.