• Nuclear Engineering and Technology
• /
• 제55권1호
• /
• pp.222-228
• /
• 2023

This study aimed to analyze the applicability of the improved median filter in positron emission tomography (PET)/magnetic resonance (MR) fusion images based on parallel imaging using generalized autocalibrating partially parallel acquisition (GRAPPA). In this study, a PET/MR fusion imaging system based on a 3.0T magnetic field and ¹⁸F radioisotope were used. An improved median filter that can set a mask of the median value more efficiently than before was modeled and applied to the acquired image. As quantitative evaluation parameters of the noise level, the contrast to noise ratio (CNR) and coefficient of variation (COV) were calculated. Additionally, no-reference-based evaluation parameters were used to analyze the overall image quality. We confirmed that the CNR and COV values of the PET/MR fusion images to which the improved median filter was applied improved by approximately 3.32 and 2.19 times on average, respectively, compared to the noisy image. In addition, the no-reference-based evaluation results showed a similar trend for the noise-level results. In conclusion, we demonstrated that it can be supplemented by using an improved median filter, which suggests the problem of image quality degradation of PET/MR fusion images that shortens scan time using GRAPPA.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.473-476
• /
• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• 한국연소학회:학술대회논문집
• /
• 한국연소학회 2001년도 제22회 KOSCI SYMPOSIUM 논문집
• /
• pp.156-162
• /
• 2001

The effects of co-flow and the variation of the equivalence ratio on NOx emission were investigated experimentally for unconfined and confined partially premixed flames. The shape, length, temperature of flames and the concentration of burnt gas were measured. Two types of co-flow (parallel and swirling co-flow) were considered. For unconfined flames, flame with parallel co-flow is the longest and the next is flame without co-flow. Flame with swirl is the shortest. The length of swirling flame increases suddenly under certain value of equivalence ratio. EINOx is diminished by the decrease of equivalence ratio. It is found that the unconfining of flame enhances the emission of NOx. The EINOx of unconfined flame with parallel co-flow is less than that of flame without co-flow.

• 품질경영학회지
• /
• 제24권4호
• /
• pp.14-28
• /
• 1996

We consider optimal designs of partially accelerated life testing which is deviced for parallel systems with the considerably long life time. In partially step-stress life testing, test items are first run simultaneously at use condition for a specified time, and the surviving items are then run at accelerated condition until a predetermined censoring time. In partially constant-stress life testing, test items are run at either use or accelerated condition only until a specified censoring time. The optimal criterion for each test is to minimize either the generalized asymptotic variance of maximum likelihood(ML) estimators of the hazard rates at use condition and the acceleration factors or the asymptotic variance of the ML estimators of the acceleration factors.

• 전기전자학회논문지
• /
• 제23권4호
• /
• pp.1288-1294
• /
• 2019

Polar code의 채널용량 달성 특성은 polar code를 각광 받는 오류 정정 부호로 만들었다. 하지만 충분한 오류 정정 성능은 부호의 길이가 길어졌을 때 달성되는 점근적 속성을 보인다. 따라서 입력 데이터가 길어지는 경우에 대한 초대규모 집적회로 구현을 실현하기 위하여 효율적인 구조가 필요하게 되었다. 기존의 polar code 부호기 구조 중 가장 기본적인 완전 병렬 구조는 직관적이고 구현이 쉽지만 긴 polar code에 높은 하드웨어 복잡성을 보이므로 부적합하다. 그리고 이를 보완하여 제안된 부분 병렬 구조는 하드웨어 면적 측면에서 큰 성과를 얻었으나 그 방식이 일반화되어 있지 않아 설계자에 따라 구조에 변동이 발생할 수 있다. 본 논문에서는 이를 개선하고자 비트 차원의 치환을 위해 제안된 회로 설계법을 polar code에 적용하는 하드웨어 설계법을 제안한다. 제안하는 방법을 polar code의 부호기에 적용함으로써 완전 병렬 부호기만큼 직관적인 구조를 가짐과 동시에 일반화된 polar code 부분 병렬 부호기를 설계할 수 있다.

• 대한설비공학회:학술대회논문집
• /
• 대한설비공학회 2008년도 동계학술발표대회 논문집
• /
• pp.9-14
• /
• 2008

The effects of baffles in PEM fuel cell with parallel flow channel has been simulated by using conmmercial program. The simulation has been conducted through the channel and there are four different heights of baffles, No Baffle($H_b$=0), Partially Blocked Baffle(0.25, 0.5, 0.75), Fully Blocked Baffle(1) conditions. The result shows that current density changes while placing a baffle at the various positions along the channel. Current density with a single baffle is higher than that without baffle and current density using Fully Blocked Baffle(FBB) is much higher than current density using Partially Blocked Baffle(PBB). When the baffle is closer to outlet of the channel, current density increases. It is found that pressure is related to current density. If the pressure is higher, the better performance will be expected.

• 한국정보전자통신기술학회논문지
• /
• 제4권4호
• /
• pp.278-285
• /
• 2011

본 논문에서는 DVB-S2 표준안에서 권고되고 있는 irregular LDPC 부호의 다양한 부호화율에서 부호화 방식 및 복호화 방식에 대해 살펴보고 이에 대한 성능분석을 하였다. 또한 이의 구현에 있어서 효율적인 메모리 할당 및 이에 따른 구현 방법에 대해 연구하였다. LDPC 복호기를 구현하는 방안에는 직렬, 부분병렬, 완전병렬 방식이 있으며, 부분병렬방식이 하드웨어 복잡도와 복호속도를 절충하는 방안이다. 따라서 본 논문에서는 부분병렬 구조를 기반으로 하는 LDPC 복호기의 메모리 설계에서 효율적인 체크노드, 비트노드, LLR 메모리의 구조를 제안하고저 한다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권4호
• /
• pp.419-426
• /
• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2017년도 춘계학술발표대회
• /
• pp.64-67
• /
• 2017

Applying concurrent structure and parallel processing are a common issue for these day's programs. In this research, Dynamic Programming is used to compare the parallel performance of Go language and Intel C++ Thread Building Blocks. The experiment was performed on 4 core machine and its result contains execution time under Simultaneous Multi-Threading environment. Static Optimal Binary Search Tree was used as an example. From the result, the speed-up of Go was higher than the number of cores, and that of TBB was close to it. TBB performed better in general, but for larger scale, Go was partially faster than the other.

• 한국윤활학회:학술대회논문집
• /
• 한국윤활학회 1999년도 제30회 추계학술대회
• /
• pp.136-145
• /
• 1999

This paper describes the surface roughness effect in parallel thrust bearing. In mixed lubrication, some contacts will take place between asperities, and partial lubrication will occur. An average Reynolds Equation is utilized to determine effects of surface roughness on partially lubricated contacts. By using an autocorrelation function for the surface profile, surface model is generated numerically Although the two surfaces are parallel in thrust bearing separated by thin film, the pressure peak is formed due to asperites. By means of surface profile parameters, it is shown that which surface is optimal for the parallel thrust bearing.