• Title/Summary/Keyword: Parasitic inductance

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Design of Variable Active Inductor with Feedback LC-Resonator for Improvement of Q-Factor and Tuning of Operating Frequency (Q 지수의 개선과 동작 주파수 조절을 위해 궤환 LC-공진기를 이용한 가변 능동 인덕터의 설계)

  • Seo, Su-Jin;Ryu, Nam-Sik;Choi, Heung-Jae;Jeong, Yong-Chae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.3
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    • pp.311-320
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    • 2008
  • In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.

Dual-Band Power Divider Using CRLH-TL (CRLH 전송 선로 구조를 이용한 이중 대역 전력 분배기)

  • Kim, Seung-Hwan;Sohn, Kang-Ho;Kim, Ell-Kou;Kim, Young;Lee, Young-Soon;Yoon, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.8
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    • pp.837-843
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    • 2008
  • This paper proposes a power divider based on meta-material structure with dual-band operation. The meta-material structures of left-hand characteristic are constituted of series capacitors and shunt inductors, but they have parasitic series inductance and shunt capacitance effects. There is represented the composite right/ left-handed transmission line (CRLH-TL) model. When the power divider is implemented by using the CRLH-TL, the power divider can operate dual band. To verify the power divider with dual band, we are implemented to operate dual-band that is 0.88 GHz and 1.67 GHz. The characteristics of divider have the return loss less than each 21.0 dB and 15.8 dB and the insertion loss better than 3.83 dB and 3.64 dB at each frequency. Also, the output phase difference is $3{\sim}6^{\circ}$.

Composite EBG Power Plane Using Magnetic Materials for SSN Suppression in High-Speed Digital Circuits (고속 디지털 회로의 SSN 억제를 위한 자성 재료가 적용된 복합형 EBG 전원면)

  • Eom, Dong-Sik;Kim, Dong-Yeop;Byun, Jin-Do;Lee, Hai-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.8
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    • pp.933-939
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    • 2008
  • In this paper, a new composite electromagnetic bandgap(EBG) structure using magnetic materials is proposed for simultaneous switching noise(SSN) suppression in the high-speed digital circuits. The proposed EBG structure has periodic unit cells of square-patches connected by spiral-shaped bridges. The magnetic materials are located on the unit cells of spiral-shaped EBG. The real part of the permeability shifts bandgap to the lower frequency region due to the increased effective inductance. The imaginary part of the permeability has magnetic loss that decreases parasitic LC resonance peaks from between the unit cells. As a result, the proposed structure has the lower cut-off frequency compared with conventional EBG structure and -30 dB SSN suppression bandwidth from 175 MHz to 7.7 GHz. The proposed structure is expected to improve the power integrity and reduce the size of the EBG power plane.

Development of a 3 kW Grid-tied PV Inverter With GaN HEMT Considering Thermal Considerations (GaN HEMT를 적용한 3kW급 계통연계 태양광 인버터의 방열 설계 및 개발)

  • Han, Seok-Gyu;Noh, Yong-Su;Hyon, Byong-Jo;Park, Joon-Sung;Joo, Dongmyoung
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.5
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    • pp.325-333
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    • 2021
  • A 3 kW grid-tied PV inverter with Gallium nitride high-electron mobility transistor (GaN HEMT) for domestic commercialization was developed using boost converter and full-bridge inverter with LCL filter topology. Recently, many GaN HEMTs are manufactured as surface mount packages because of their lower parasitic inductance characteristic than standard TO (transistor outline) packages. A surface mount packaged GaN HEMT releases heat through either top or bottom cooling method. IGOT60R070D1 is selected as a key power semiconductor because it has a top cooling method and fairly low thermal resistances from junction to ambient. Its characteristics allow the design of a 3 kW inverter without forced convection, thereby providing great advantages in terms of easy maintenance and high reliability. 1EDF5673K is selected as a gate driver because its driving current and negative voltage output characteristics are highly optimized for IGOT60R070D1. An LCL filter with passive damping resistor is applied to attenuate the switching frequency harmonics to the grid-tied operation. The designed LCL filter parameters are validated with PSIM simulation. A prototype of 3 kW PV inverter with GaN HEMT is constructed to verify the performance of the power conversion system. It achieved high power density of 614 W/L and peak power efficiency of 99% for the boost converter and inverter.

Wideband Colpitts Voltage Controlled Oscillator with Nanosecond Startup Time and 28 % Tuning Bandwidth for Bubble-Type Motion Detector (나노초의 발진 기동 시간과 28 %의 튜닝 대역폭을 가지는 버블형 동작감지기용 광대역 콜피츠 전압제어발진기)

  • Shin, Im-Hyu;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.11
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    • pp.1104-1112
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    • 2013
  • This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

Stacked Pad Area Away Package Modules for a Radio Frequency Transceiver Circuit (RF 송수신 회로의 적층형 PAA 패키지 모듈)

  • Jee, Yong;Nam, Sang-Woo;Hong, Seok-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.10
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    • pp.687-698
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    • 2001
  • This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

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Radio Frequency Circuit Module BGA(Ball Grid Array) (Radio Frequency 회로 모듈 BGA(Ball Grid Array) 패키지)

  • Kim, Dong-Young;Jung, Tae-Ho;Choi, Soon-Shin;Jee, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.8-18
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    • 2000
  • We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers

  • Moon, Dae-Ho;Ha, Tae-Min;Kim, Boom-Soo;Han, Seung-Soo;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.431-432
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    • 2012
  • In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

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Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process (pHEMT 공정을 이용한 저손실, 고전력 4중 대역용 SP6T 스위치 칩의 설계 및 제작)

  • Kwon, Tae-Min;Park, Yong-Min;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.584-597
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    • 2011
  • In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.