• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.250-256
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• 2007

We analyzed the effect of a pixel and all the inter-electrode capacitances in a unit pixel of TFT-LCDs on the gray scale capability. The pixel and all the inter-electrode parasitic capacitances were obtained from the tree dimensional profiles of potential distribution and molecular director considering lateral fields generated at the edge of the pixel. To obtain the RMS and kickback voltages of the pixel, we constructed an equivalent circuit of the panel containing all the parasitic capacitances. The calculation was performed though H-SPICE. As results, we confirmed that the pixel becomes smaller, the effect of parasitic capacitances on the gray scale capability becomes larger.

• Journal of Power Electronics
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• v.16 no.1
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• pp.374-387
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• 2016

This paper derives an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of SiC MOSFETs. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of the trans-conductance. The turn-on process and the turn-off process are illustrated in detail, and equivalent circuits are derived and solved for each switching transition. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. Note that switching losses calculated based on experiments are imprecise, because the energy of the junction capacitances is not properly disposed. Finally, the proposed analytical model is utilized to account for the effects of parasitic elements on the switching performance of a SiC MOSFET, and the circuit design rules for high frequency circuits are given.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of Sensor Science and Technology
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• v.21 no.3
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• pp.235-239
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• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.10-16
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• 2003

To analyze the effects of the air-bridge parasitic capacitances on the performance of coplanar waveguide pseudomorphic high electron mobility transistors (CPW PHEMTs), the gate-to-air-bridge ( $C_{ag}$ ) and the drain-to air-bridge ( $C_{ad}$ ) capacitances were taken into account plus the conventional pinched-off cold. FET circuit model. To examine the effects of the parasitic capacitances due to the air-bridges, a variety routing schemes for the air-bridge interconnection were adopted for fabricating the 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate length CPW HEMT's. According to air-bridge schemes, the $S_{21}$ gain is affected considerably. From the results of the fabricated CPW PHEMT, the $C_{ag}$ and $C_{ad}$ is one of the important factor of decreasing the gain of HEMTs.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.55-57
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• 2005

This paper deals with the analysis of bearing current in H-bridge seven level multilevel inverter fed induction motor. In the previous researches utilized electromagnetic equations to derive the parasitic capacitance or measured capacitance parameters, but we used FEM to derive parasitic capacitances and defined the equivalent circuit parameters in our strategy. Then we compared suggested method with conventional method in 60 [Hz] no load condition.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.522-530
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• 2018

This study proposes the mitigation method of shaft voltage by varying the parasitic capacitance. First, the shaft voltage explained. Second, the parasitic capacitances causing shaft voltage are analyzed respect to geometry of motor and windings. Then, the equivalent circuit is established to obtain the shaft voltage and output torque characteristic and develope appropriate motor structure. Finally, simulation and experiment are conducted to verify that modified motor suppress the shaft voltage. This novel model does not require additional hardware.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.187-191
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• 2009

Recently, we have used LEDs to illumination because it has a high luminous efficiency and prolong lifespan. However the light power and lifetime is reduced by junction temperature increment of LED. So it is important to measure the junction temperature accurately. In case of using a electrical method measuring junction temperature of LED. Temperature measurement errors are spontaneously generated because of a parasitic capacitances in LED. In this paper, we proposed a method that reducing LED's parasitic capacitance effects for electrical measurement. It was demonstrated by the experimental result that is more correct than established method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.