• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.547-548
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• 2006

In this paper, cost effective parallel-branch inductor has been proposed and developed in order to increase the quality factor of the conventional spiral inductor. This parallel-branch inductor is composed of only two metals. The presented parallel-branch inductor shows 12% improvement in the quality factor with the same area as the conventional inductor. Also, we improve the parallel-branch inductor for high frequency applications.

• Journal of electromagnetic engineering and science
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• v.8 no.2
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• pp.47-51
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• 2008

In this paper, we present a cost effective parallel-branch spiral inductor with the enhanced quality factor and the resonance frequency. This structure is designed to improve the quality factor, but different from other fully stacked spiral inductors. The parallel-branch effect is increased by overlapping the first metal below the second metal with same direction. Measurement result shows an increased quality factor of 12 % improvement. Also, we show an octagonal parallel-branch inductor which reduces the parasitic capacitances for higher frequency applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.89-93
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• 2002

In the present paper we suggested a parallel-branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on P-type silicon wafer (5∼15 Ω-cm) under the standard CMOS process and it showed a improved quality(Q) factor by more than 10% with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with those of the conventional spiral inductors.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.213-216
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• 2004

This paper describes design and implementation of the 5.5 GHz VCO with parallel-branch inductors using 0.8${\mu}m$ SiGe HBT process technology. The proposed parallel-branch inductor shows $12 \%$ improvement in quality factor in comparison with the conventional inductor. A phase noise of -93 dBc/Hz is measured at 100 kHz offset frequency, and the harmonics in the VCO are suppressed less than -23 dBc. The single-sided output power of the VCO is -6.5$\pm$1.5 dBm. The manufactured VCO consumes 15.0 mA with 2.5 V supply voltage. Its chip areas are 1.8mm ${\times}$ 1.2mm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.83-87
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• 2003

In the present paper we suggested a parallel branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on p-type silicon wafer (5∼15Ω-cm) under the standard CMOS process and it showed a enhanced qualify(Q) factor by more than 10 % with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with conventional spital inductors

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.3
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• pp.339-353
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• 2014

A straightforward method for optimal determining of a high frequency inductor's parasitic capacitance is presented. The proposed estimation method is based on measuring the inductor's impedance samples over a limited frequency range bordering on the resonance point considering k-dB deviation from the maximum impedance. An optimized solution to k could be obtained by minimizing the root mean squared error between the measured and the estimated impedance values. The model used to provide the estimations is a parallel RLC circuit valid at resonance frequency which will be transferred to the real model considering the mentioned interval of frequencies. A straightforward algorithm is suggested and programmed using MATLAB which does not require a wide knowledge of design parameters and could be implemented using a spectrum analyzer. The inputs are the measured impedance samples as a function of frequency along with the diameter of the conductors. The suggested algorithm practically provides the estimated parameters of a real inductance model at different frequencies, with or without design information. The suggested work is different from designing a high frequency inductor; it is rather concentration of determining the parameters of an available real inductor that could be easily done by a recipe provided to a technician.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1187-1194
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• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.422-422
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• 2004