• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.213-216
• /
• 2004

This paper describes design and implementation of the 5.5 GHz VCO with parallel-branch inductors using 0.8${\mu}m$ SiGe HBT process technology. The proposed parallel-branch inductor shows $12 \%$ improvement in quality factor in comparison with the conventional inductor. A phase noise of -93 dBc/Hz is measured at 100 kHz offset frequency, and the harmonics in the VCO are suppressed less than -23 dBc. The single-sided output power of the VCO is -6.5$\pm$1.5 dBm. The manufactured VCO consumes 15.0 mA with 2.5 V supply voltage. Its chip areas are 1.8mm ${\times}$ 1.2mm.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.1
• /
• pp.75-81
• /
• 2017

This paper presents a design and parallel control strategy of 1.8 kW low-voltage DC-DC converter (LDC) for mild hybrid electric vehicles to improve their power density, system efficiency, and operation stability. Topology and control scheme are important on the LDC for mild hybrid electric vehicles to achieve high system efficiency and power density because of their very low voltage and large current in input and output terminals. Therefore, the optimal topological structure and control algorithm are examined, and a detailed design methodology for the power and control stages is presented. A working sample of 1.8 kW LDC is designed and implemented by applying the adopted topology and control strategy. Experimental results indicate 92.45% of the maximum efficiency and 560 W/l of power density.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.12
• /
• pp.723-731
• /
• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Applied Microscopy
• /
• v.46 no.1
• /
• pp.6-13
• /
• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.1
• /
• pp.57-64
• /
• 2000

We describe a parallel implementation for the large-eddy simulation(LES) of stratified and rotating turbulence based on MPI. The parallelization strategy is specified by eliminating the tridiagonal solver with explicit method and by domain decompositions for solving the poisson equation. In this simulation we have run on CRAY-T3E under the message passing platform MPI with a various domain decomposition and the scalability of this parallel code of LES are also presented. The result shows that we can gain up to 16 times faster speed up on 64 processors with xyz-directional domain decomposition and scalable up to $128{\times}128{\times}$ which processing time is almost similar to that of $40{\times}40{\times}40$ on a single processor machine with a sequential code.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.16 no.5
• /
• pp.47-54
• /
• 2017

This study examines the implementation of a kinematic machining tool to evaluate the interference and collision phenomenon of 5-axis machining of wing ribs from airplanes, particularly for a large-size model airplane. We develop a machine simulation model of a parallel kinematic machining tool that can operate in a virtual space, which is equivalent to the authentic conditions in the field. The investigation of the simulation function elements indicates the necessity to generate the 6-axis machining, which attaches an angle head to the main axis of the machine. Using an NC program for the wing ribs, we attempt to verify the correspondence and conformity between the machine simulation model and the actual equipment.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.2
• /
• pp.11-17
• /
• 2008

The net shape effects by the various vectors in underwater. Each particle of the net calculating the effect of all vectors augments an accuracy and reality. But, the time complexity becomes larger because of huge calculation. The previous techniques reduced a physics reality. And embodied the underwater virtual reality which augments visual reality with simulation. In this paper, parallel processing the particles, it embodied the simulation which is satisfied a physical reality and time reality. The parallel processing used the OpenMP, and the reality graphic expression used the OpenGL. The simulation which this paper Proposes will be the possibility becoming the fundamental data for a model analysis or a specialist system from game and marine field.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.9
• /
• pp.531-538
• /
• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• The KIPS Transactions:PartB
• /
• v.8B no.1
• /
• pp.89-97
• /
• 2001

대용량 멀티미디어 미디어 서버를 구성함에 있어 I/O 병목현상을 극복하기 위하여 저장 서버들과 제어 서버로 구성되어진 2계층 분산 클러스터 서버구조가 많이 사용된다. 2 계층 분산 클러스터 서버는 부하 균등, 대역폭 관리 및 저장 서버의 관리 측면에서 유리한 반면, 저장 서버와 제어 서버간의 통신 오버헤드를 발생시킨다. 이러한 오버헤드를 줄이기 위해서는 저장 서버에서 읽은 미디어 데이터를 제어 서버를 거치지 않고 직접 클라이언트에 전송할 수 있어야 한다. 그리고, 저장 용량을 확장하거나 손상된 디스크를 교체하는 경우를 대비하여 분산 클러스터 서버는 다양한 성능의 이기종 디스크를 지원하여야 한다. 또한, I/O 장치와 운영체제가 빠르게 발전됨에 따라 미디어 서버는 새로운 I/O 장치 및 운영체제 등에 쉽게 이식될 수 있어야 하고, 응용 소프트웨어 개발자가 시스템의 환경에 따라 블록크기, 데이터 배치정책, 사본 정책 등을 유연하게 조절할 수 있어야 한다. 본 논문에서 위에서 언급한 멀티미디어 서버의 요구를 고려하여 Fast Ethernet 환경에서 병렬 멀티미디어 파일 시스템(PMFS : Parallel Multimedia File System)을 설계 및 구현하고 실험을 통해 PVFS(Parallel Virtual File System)와 성능을 비교 분석하였다. 이 실험의 결과에 따르면 PMFS는 멀티미디어 데이터에 대하여 PVFS보다 3%∼15%의 향상된 성능을 보였다.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.11
• /
• pp.2690-2700
• /
• 1997

This paper presents parallel sorting algorithm, SHARED-MEMORY-BS and REDUCED-BS, which are implemented on shared-memory parallel computers. These algorithm sort N keys in $O(log^2N)$ time. REDUCED-BS users a parity strategy which gives an idea for the efficient usage of the local memory associated with each processor. By taking advantage of the local memory associated with each processor, the communication of REDUCED-BS is decreased by approximately half that of SHARED-MEMORY-BS. On the basis of alleviating the communication, the algorithm REDUCED-BS results in a significant improvement of performance.