• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.2
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• pp.20-28
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• 2003

Recently we need a faster and more accurate motion vector search algorithm for ASIC(Application Specific IC) or small systems. Block motion estimation using Full Search(FS) algorithm provides the best visual quality and PSNR, but it requires intensive computations. The previously proposed fast algorithms reduced the number of computations by limiting the number of searching locations. This is accomplished at the expense of less accuracy of motion estimation and gives rise to an appreciably higher SAD(Sum of Absolute Difference) for motion compensated images. In this paper we exploit the spatial correlation of motion vectors and present a fast motion estimation scheme which uses the predicted motion vector(PMV). The PMV scheme is more clear and simpler than the previously proposed algorithms which also use adjacent motion vectors. Simulation results with standard video sequences show that the PMV scheme is faster and more accurate than other algorithms such as Nearest-Neighbors Search(NNS) algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.494-503
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• 2002

A motion vector re-estimation algorithm for image downscaling in discrete consine transform domain is presented. Kernel functions are difined using SAD (Aum of Absolute Difference) and edge information of a macroblock. The proposed method uses these kernel functions to re-estimate a new motion vector of the downscaled image. The motion vectors from the incoming bitstream of transcoder are reused to reduce computation burden of the block-matching motion estimation, and we also reuse the given motion vectors. Several experiments in this paper show that the computation efficiency and the PSNR (Peak Signal to Noise Ratio) and better than the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.6
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• pp.123-131
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• 2009

The emerging display technology has been replaced the previous position of the CRT with the LCD. The nature of hold type display such as LCD, however, causes many problems such as motion blur and motion judder. To resolve the problems, we used frame interpolation technique which improves the image quality by inserting new interpolated frames between existing frames. In this paper, we propose a novel frame interpolation technique that uses dominant MV and variance different value in each block. At first, the proposed algorithm performs unidirectional motion estimation using blocking matching algorithm. The new frame is generated by pixel average using compared block variance or by pixel motion compensation using dominant motion vector, whether the motion estimation find the target area or not. Several experiments with the proposed algorithm shows that the proposed algorithm has better image quality than the existing bidirectional frame interpolation algorithm at the rate of about 3dB PSNR and has low complexity comparing to the unidirectional frame interpolation technique.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.27 no.1
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• pp.54-61
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• 2023

With the development of IoT technologies and artificial intelligent, diverse digital image equipments are being used in industrial sites. Because image data can be easily damaged by noise while it's obtained with a camera or a sensor and the damaged image has a bad effect on the process of image processing, noise removal is being demanded as preprocessing. In this thesis, for the restoration of image damaged by the noise of random impulse, a switching filter algorithm based on noise estimation was suggested. With the proposed algorithm, noise estimation and error distraction were carried out according to the similarity of the pixel values in the local mask of the image, and a filter was chosen and switched depending on the ratio of noise existing in the local mask. Simulations were conducted to analyze the noise removal performance of the proposed algorithm, and as a result of magnified image and PSNR comparison, it showed superior performance compared to the existing method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.143-146
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• 1998

A new stereoscopic codec. structure using MPEG-2 multiview profile is presented in this paper. In the suggested codec., the left image is coded with motion estimation in the base layerand the right image is coded with disparity estimation in the enhancement layer. Since it is possible to calculate rough motion of the right image sequence with disparity and motion of the left image sequence, motion compensation of the enhancement layer is performed without motion estimation. Since the proposed codec. does not perform motion estimation in the enhancement layer encoding, it is simple and reduces the encoding time. We compared the PSNR of encoded image with three different structured codec., and the experimental results show that suggested codec. has comparable with other codecs.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.53-59
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• 2014

Motion estimation is a core part of most video compression systems since it directly affects the output video quality and the encoding time. The full search (FS) technique gives the highest visual quality but has the problem of a significant computational load. To solve this problem, we present in this paper a modified median (MMED) operation and advanced search strategies for fast motion estimation. The proposed MMED operation includes a temporally co-located motion vector (MV) to select an appropriate initial candidate. Moreover, we introduce a search procedure that reduces the number of thresholds and simplifies the early termination conditions for the determination of a final MV. The experimental results show that the proposed approach achieves substantial speedup compared with the conventional methods including the motion vector field adaptive search technique (MVFAST) and predictive MVFAST (PMVFAST). The proposed algorithm also improves the PSNR values by increasing the correlation between the MVs, compared with the FS method.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.104-115
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• 1993

The motion compensated coding (MCC) technique, which exploits the temporal redundancies in the moving images with the motion estimation technique,is one of the most popular techniques currently used. Recently, a variable block size(VBS) motion estimation scheme has been utilized to improve the performance of the motion compensted coding. This scheme allows large blocks to the used when smaller blocks provide little gain, saving rates for areas containing more complex motion. Hence, a new VBS motion estimation scheme with a hierarchical structure is proposed in this paper, in order to combine the motion vector coding technique efficiently. Topmost level motion vector, which is obtained by the gain/cost motion estimation technique with selective motion prediction method, is always transmitted. Thus, the hierarchical VBS motion estimation scheme can efficiently exploit the redundancies among neighboring motion vectors, providing an efficient motion vector encoding scheme. Also, a restricted search with respect to the topmost level motion vector enables more flexible and efficient motion estimation for the remaining lower level blocks. Computer simulations on the high resolution image sequence show that, the VBS motion estimation scheme provides a performance improvement of 0.6~0.7 dB, in terms of PSNR, compared to the fixed block size motion estimation scheme.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.2
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• pp.69-76
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• 2010

This paper proposed a new fast multi-reference frame motion estimation algorithm. The proposed algorithm reduces search areas of motion estimation using a linear relation of motion vector with distance of each reference frame. New algorithm executes full search area motion estimation in reference frame 0 and reference frame 1. After that, search areas in reference frame 2, reference frame 3 and reference frame 4 are minimized by distance of each reference frame and results of motion estimation in reference frame 0 and reference frame 1. The proposed algorithm does not use a threshold value which is obstacle of hardware implementation and processing time schedule. Also, it reduced computation quantity of multi-reference motion estimation. Hardware implementation of multi-reference frame motion estimation is possible by these features. Simulation results show that PSNR drop and bitrate increase of proposed algorithm are lower than those of previous fast multi-reference frame motion estimation algorithm The number of computation of new algorithm is reduced 52.5% and quality of result is negligible when compared with full search area motion estimation which has 5 reference frames.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).