• Title/Summary/Keyword: PNP

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Serratia marcescens Purine Nucleoside Phosphorylase의 정제 및 특성 (Purification and Properties of Serratia marcescens Purine Nucleoside Phosphorylase.)

  • 방성권;신종란;최병범
    • 한국미생물·생명공학회지
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    • 제28권5호
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    • pp.251-257
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    • 2000
  • Serratia marcescens purine nucleoside phosphorylase (PNP) was purfied to homogeneity by streptomycin sulfate treatment, Sephacry HR S-200 gel filtration chromatography and AMP-agarose affinity chromatography. The specific activity of the enzyme was increased 49-fold during purification with an overall yield of 7.0%. The molecular weight was 168kD as estimated by Sephadex G-150 gel filtration chromatography. The S. marcescens enzyme was composed of six identical subunits with subunit molecular weight of 28kD, as estimated by SDS-PAGE. The Km values of S. marcescens enzyme for inosine and deoxyinsoine were 0.38 and 1.20 mM, respectively. The ph optimum was near 8.0, and the enzyme was relatively heat-stable protein. The enzyme was inactivated com-pletely by 0.5 mM of $Cu^{ 2+}$.

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고전압 GCT(Gate Commutated Thyristor) 소자 설계 (A Novel Design for High Voltage RC-GCTs)

  • 장창리;김상철;김은동;김형우;서길수;김남균
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.312-315
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    • 2003
  • Basic design of RC-GCTs (Reserve-Conducting Gate-Commutated Thyristors) by novel punch-through (PT) concept with 5,500v rated voltage is described here. A PT and NPT (non punch-through) concept for the same blocking voltage has been compared in detail. The simulation work indicates that GCT with such PT design exhibits that the forward breakdown voltage is 6,400V which is enough for supporting 5500V blocking. Additionally, the real IGCT turn-off in the mode of PNP transistor has been realized. However, the carrier extraction from N-base to gate terminal will be drastic slowly in terms of NPT structure except for the high on-state voltage drop.

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에너지 변환을 이용한 근접센서에의 적용 (Application of Proximity Sensor using Energy Transformation)

  • 이용제;이교성;김도훈;오세호;김양모
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.237-240
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    • 2002
  • We have studied a RF energy transformation. In this paper, we introduced proximity sensor using RF energy transformation. We used 125kHz RF signal as carrier frequency and BPSK circuit, PNP proximity sensor and designed circuit to transmit to the reader through the antenna with data which sensor had acquired. Micro-controller, oscillator, power amp, FSK Modulation module are included in the circuit. Max 323 chip is applied to analog switch and used to HYP-30R10NA sensor chip.

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Effects of Platinum Nanoparticles on the Postnatal Development of Mouse Pups by Maternal Exposure

  • Park, Eun-Jung;Kim, He-Ro;Kim, Young-Hun;Park, Kwang-Sik
    • Environmental Analysis Health and Toxicology
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    • 제25권4호
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    • pp.279-286
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    • 2010
  • Objectives : Platinum nanoparticles (PNPs) are potentially useful for sensing, catalysis, and other applications in the biological and medical sciences. However, little is known about PNP toxicity. In this study, adverse effects of PNPs on the postnatal development of mouse pubs were investigated. Methods : PNPs (size: 20 nm) were prepared and orally administered to mice during premating, gestation, and lactation periods (0.25 mg/kg, 0.5 mg/kg, and 1 mg/kg). Maternal and pup toxicity were evaluated. Results : PNPs did not affect blood biochemical parameters or mortality in dams during the experimental period. Histopathological signs were not observed and pup number was not different between the control and treated groups. Deformity and stillbirth were not observed in the pups. However, PNPs increased pup mortality and decreased the infant growth rate during the lactation period. Conclusion : PNPs may have adverse effects to the postnatal development of mouse pups.

CMOS Latch-Up 현상의 실험적 해석 및 그 방지책 (Experimental Analysis and Suppression Method of CMOS Latch-Up Phenomena)

  • 고요환;김충기;경종민
    • 대한전자공학회논문지
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    • 제22권5호
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    • pp.50-56
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    • 1985
  • A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

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IGBT 설계 Parameter 연구 (A Study on Parameters for Design of IGBT)

  • 노영환;이상용;김윤호
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2009년도 춘계학술대회 논문집
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    • pp.1943-1950
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    • 2009
  • The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

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속도 향상을 위한 병합트랜지스터를 이용한 ISL의 설계 (Design of ISL(Intergrated Schottky Logic) for improvement speed using merged transistor)

  • 장창덕;백도현;이정석;이용재
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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    • pp.21-25
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    • 1999
  • In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

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2.5V $0.25{\mu}m$ CMOS Temperature Sensor with 4-Bit SA ADC

  • 김문규;장영찬
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 추계학술대회
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    • pp.448-451
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    • 2011
  • SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

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비정상 몰분율 효과에 대한 동역학적 격자기반 대정준 Monte Carlo 모의실험 연구

  • 여혜진;황현석
    • EDISON SW 활용 경진대회 논문집
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    • 제5회(2016년)
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    • pp.102-107
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    • 2016
  • 본 연구에서는 동역학적 격자기반 대정준 Monte Carlo (Kinetic Lattice Grand Canonical Monte Carlo, KLGCMC) 모의실험 방법을 이용하여 비정상 몰분율 효과 (Anomalous mole fraction effect)에 대해서 알아보고자 하였다. 이를 위해 양이온 선택성을 가진 이온채널 모델에서 $NH_4{^+}$$Rb^+$의 혼합물에 대하여 몰분율의 변화에 따른 이온전도도를 KLGCMC 모의실험을 이용하여 계산하고, 이를 평균장 이론인 Poisson-Nernst-Planck (PNP)의 결과와 비교해 봄으로써 비정상 몰분율 효과에 대하여 심도 있게 이해하고자 하였다. 본 연구 결과로부터 비정상 몰분율 효과는 이온채널의 이온 선택성에 의해서 발생함을 확인할 수 있었다. 즉, 두 종류 이상의 이온들이 채널 내부로 이동할 때, 이온채널의 이온 선택성에 의해서 각 이온들과 채널 간에 서로 상이한 상호작용을 하게 되고, 이로 인해서 이온 혼합물 조성의 변화, 즉 몰분율의 변화에 대해서 이온 전류가 선형적이 아닌 비선형적으로 변하게 됨을 알 수 있었다.

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앨범제작을 위한 편집시스템 설계 (Design of Edit System for Album Production)

  • 정병완;한군희;최신형
    • 한국산학기술학회:학술대회논문집
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    • 한국산학기술학회 2007년도 추계학술발표논문집
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    • pp.99-101
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    • 2007
  • 사진관과 인쇄소간의 역할분담, 급속한 인터넷의 발달과 고속 인쇄기의 보급으로 노동집약적인 졸업 앨범 제작은 누구나 손쉽게 문서를 원하는 형태로 제작 출력이 가능해 졌다. 하지만 명함이나 광고 전단지, 신문이나 잡지, 전화번호부 책자 및 소책자를 제작하기 위해서는 전용 편집용 소프트웨어를 이용하여 전문가들이 제작을 하고 있다. 본 논문에서는 가장 대표적인 광고도안인 명함을 인터넷을 이용하여 신청단계부터 PDF파일을 생성하는 단계까지 일련의 작업공정을 자동화시스템을 구축하기 위한 컴퓨터조판시스템의 모델을 제시한다.

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