• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.396-399
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• 2003

4H-SiC un diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base region and p+ region in the n-epilayer. We have obtained up to 1782V of reverse breakdown voltage in the un diode with two FLRs on loom thick epilayer. The differential on-resistances of the fabricated diode are $5.3m{\Omega}cm^2$ at $100A/cm^2$ and $2.7m{\Omega}cm^2$ at $1kA/cm^2$, respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than that of diode without an FLR. Regardless of the activation temperature, the un diode with a FLR located 5um apart from main junction has the highest mean breakdown voltage around 1600V among the diodes with one ring. On the other hand, the pn diode with two rings showed different behavior with activation temperature. It reveals that high voltage SiC pn diodes with low on-resistance can be fabricated by using the FLR edge termination.

• 전자공학회논문지A
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• 제31A권12호
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• pp.100-105
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• 1994

SOI(Silicon-On-Insulator) pn 다이오드의 최적 수평길이($L_{dr}$)와 항복전압에 대한 해석적인 표현식을 n' 츠리프트 영역의 농도 및 두께, 매몰 산화막 두께의 함수로 유도하였다. 최적($L_{dr}$은 n'n접합의 수직 방향전계에 의한 항복전압과 n'np'접합으 수평방향 전계에 의한 항복전압이 같다는 조건으로부터 유도하였다. 해석적 표현식의 결과는 PISCESII를 사용한 시뮬레이션 결과와 잘 일치하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.612-615
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• 2004

A high-voltage generator is used to program the anti-fuse of the semiconductor chip. A new high-voltage generator consists of PN diodes and new stack type capacitors. An oscillator supply pulses to the high-voltage generator. The pulse period of the oscillator is delayed by controlling gate-voltage of the MOS. The pulse period is about 27ns, therefore the pulse frequency is about 37MHz. The threshold voltage of PN diode is about 0.8V. The capacitance of new stack type capacitor is about 4pF. The output voltage of the new high-voltage generator is about 7.9V and its current capacity is about $488{\mu}$A.

• 대한전자공학회논문지SD
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• 제46권6호
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• pp.1-5
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• 2009

6H-SiC 전자 및 정공의 이온화계수로부터 유효이온화계수를 추출하여 6H-SiC PN 다이오드의 항복전압과 온-저항을 위한 해석적 표현식을 유도하였다. 해석적 모형으로부터 구한 항복전압을 $10^{15}{\sim}10^{18}\;cm^{-3}$의 도핑 농도 범위에서 실험 결과와 비교하여 10% 이내의 오차로 일치하였고, 농도 함수의 온-저항의 해석적 결과도 $5{\times}10^{15}{\sim}10^{16}\;cm^{-3}$의 범위에서 이미 발표된 수치적 결과와 매우 잘 일치하였다.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.39-43
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• 2017

It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

• 전기전자학회논문지
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• 제26권2호
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• pp.306-312
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• 2022

서로 다른 PN 비율과 금속화 어닐링 온도에 의해 장벽 높이가 다른 4H-SiC 병합 PiN Schottky(MPS) 다이오드의 전기적 특성과 심층 트랩을 조사했다. MPS 다이오드의 장벽 높이는 IV 및 CV 특성에서 얻었다. 전위장벽 높이가 낮아짐에 따라 누설 전류가 증가하여 10배의 전류가 발생하였다. 또한, 심층 트랩(Z_1/2 및 RD_1/2)은 4개의 MPS 다이오드에서 DLTS 측정을 통해 밝혀졌다. DLTS 결과를 기반으로, 트랩 에너지 준위는 낮은 장벽 높이와 함께 22~28%의 얕은 수준으로 확인되었다. 이는 쇼트키 장벽 높이에 대해 DLTS에 의해 결정된 결함 수준 및 농도의 의존성을 확인할 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1947-1949
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• 1999

Carrier lifetime in silicon power devices caused switching delay and excessive power loss at high frequency switching. We studied transient turn-on/turn-off transient characteristics of electron irradiated and proton irradiated silicon pn junction diodes. Both the electron and proton irradiation of power devices have already become a widely used practice to reduce minority carrier lifetime locally[1]. The sample is n+p junction diode, made by ion implantation on a $20\Omega.cm$ p-type wafer. We investigated turn-on/turn-off transient & breakdown voltage characteristics by digital oscilloscope. Our data show that proton irradiated samples show better performance than electron irradiated samples.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.348-351
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• 1995

A modified silicon direct bonding method has been developed alloying an intimate contact between grooved and smooth mirror-polished oxide-free silicon wafers. A regular set of grooves was formed during preparation of heavily doped $p^+$-type grid network by oxide-masking und boron diffusion. Void-free bonded interfaces with filing of the grooves were observed by x-ray diffraction topography, infrared, optical. and scanning electron microscope techniques. The presence of regularly formed grooves in bending plane results in the substantial decrease of dislocation over large areas near the interface. Moreover two strongly misoriented waters could be successfully bonded by new technique. Diodes with bonded a pn-junction yielded a value of the ideality factor n about 1.5 and the uniform distribution of series resistance over the whole area of horded pn-structure. The suitability of the modified technique was confirmed by I - V characteristics of power diodes and reversly switched-on dynistor(RSD) with a working area about $12cm^2$. Both devices demonstrated breakdown voltages close to the calculation values.

• 한국통신학회논문지
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• 제15권3호
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• pp.252-259
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• 1990

本 論文은 기존 LOCOS工程의 張點을 모두 겸비한 側面璧 SWAMI 技術에 대한 새로운 構造를 提示한다. 새로운 SWAMI공정은 순수 窒化膜 壓力과 體積 膨腸에 기인한 壓力을 크게 줄이기 위해서 側面璧 주위에 얇은 질화막과 反應性이온 飾刻으로 기울어진 실리콘 측면벽을 結合시켰따. 製作된 結果에 의하면, 缺陷이 없는 완전히 새부리 모양이 形成되지 않는 局地的 酸化 공정은 기울어진 面의 異方性 산화 隔離에 의해 實現시킬 수 있었다. 추가적인 마스크 段階는 要求되지 않는다. 이 工程에서 PN 다이오드의 漏泄電流는 기존 LOCOS 공정 보다 減少되었다. 한편 가장자리 部位는 漏泄電流 密度에서 평편한 接合 부위 보다 높게 分析되었다.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.367-371
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• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.