• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.439-440
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• 2008

A high-speed DCO is proposed that uses the negative-skewed delay scheme. The DCO consists of a ring of inverters with each PMOS transistor driven from the output of 3 earlier stage through a set of minimum-sized pass-transistors. The digitization of negative-skewed delay is achieved by selecting pass-transistors turned on and digitizing the gate voltages of the selected pass-transistors. The proposed 7-stage DCO has been simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS process to obtain a resolution of 3ps and an operation range of 2.88-5.03GHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.579-580
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• 2008

DRAM설계시 DDR2에서부터 고속 동작으로 인해 반송파에 의한 신호외곡으로 impedance matching의 필요성이 대두되었다. 이로 인해 제안된 방법은 외부 Termination 저항(RZQ)을 기준으로 impedance matching을 위한 Rtt 저항의 생성이다.[1] 제안된 ZQ Calibration 회로는 기존의conventional ZQ Calibration 회로에 After ZQ calibration block을 추가하여 한 번 더 교정함으로써 마지막 PMOS Array와 NMOS Array 저항 값이 Termination 저항 값에 가깝도록 설계하였다. 따라 전력효율은 그대로 유지하면서 ${\Delta}VM$의 오차범위를 기존의 ${\pm}5%$이내에서 skew 조건에 따라 ${\pm}1.33%$까지 향상시키는 것을 볼 수 있다. (JEDEC spec. ${\pm}5%$이내).

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.145-148
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• 2002

In this paper, a voltage controlled oscillator (VCO) with automatic amplitude control is designed using a 0.35${\mu}{\textrm}{m}$ CMOS process. A cross-coupled PMOS pair is used for a negative resistance to compensate for the losses in the LC resonator, and an automatic\ulcorner amplitude control function is adapted to provide constant output power independent of the Q-factor of the LC resonator. The designed VCO operates in the 200MHz to 550MHz frequency range using different external resonators. The simulated phase noise is -128 dBc/Hz at 100KHz offset from the carrier frequency of 260MHz. It dissipates 0.㎽ from a 3V power supply. The area is 300${\mu}{\textrm}{m}$ x1201${\mu}{\textrm}{m}$.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.78-88
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• 1992

To improve the characteristics of sub$\mu$m short channel MOSFET device, a new device having the convex structure is proposed. This device has 3-dimensionally expandable channel length according to the vertical etched silicon height. For the purpose of comparing the DC and AC characteristics, planar device is also fabricated. Comparing the channel length, the convex device with 0.4$\mu$m silicon height is larger about 0.56$\mu$m in NMOS and 0.78$\mu$m in PMOS than planar devices. DC characteristics, such as threshold voltage, operational current, substrate current and breakdown voltage are compared together with AC characteristics using the ring oscillator inverter delay. Also process and device simulation are performed and the differences between convex and pranaldevice are also compared.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.38-42
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• 2006

We report 1/f noise PSD(Power Spectrum Density) of sub-100 nm MOSFETs as a function of various parameters such as HCS (Hot Carrier Stress), bias condition, temperature, device size and types of MOSFETs. The noise spectra of sub-100 nm devices showed Lorentzian-like noise spectra. We could check roughly the position of a dominant noise source by changing $V_{DS}$. With increasing measurement temperature, the 1/f noise PSD of 50 nm PMOS device decreases, but there is no decrease in the noise of NMOS device. RTN (Random Telegraph Noise) was measured from the device that shows clearly a Lorentzian-like noise spectrum in 1/f noise spectrum.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.263-263
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• 2010

실제 옷처럼 입는 컴퓨터를 구현하거나 복잡하고 움직임이 많은 사람의 장기 등 생체에 이식 가능한 정보 전자 소자를 개발하려는 시도가 많이 이루어지고 있다. 현재는 기존의 반도체 공정과 실리콘 소재를 기반으로 연구 결과가 보고되고 있는데, 이는 소자 제작에 있어서 높은 공정 온도 등으로 인해 응용성이 제한되는 상황이다. 우리는 metal oxide 나노선과 단일벽 탄소나노튜브 (SWCNT)를 성장하여 각각 슬라이딩 전이법과 thermal tape 전이법을 이용하여 원하는 기판에 전이하고 소자를 제작하였다. metal oxide 나노선은 슬라이딩 전이를 통해 정렬된 상태로 패턴을 제작하였으며, SWCNT는 density 제어와 채널 크기 조정을 통해 반도체성 채널을 유도하여 소자 특성을 확보하였다. 또한 각 나노선의 전계효과소자와 SWCNT로 구성된 PMOS inverter를 유연한 고분자 필름기판위에 구현하고, 이를 스트레칭이 가능한 스테이지를 이용해 strain 대비 전기특성 변화를 분석하였다. 유연성이 좋은 나노선/나노튜브로 제작된 해당 소자는 전체 소자가 스트레칭이 가능할 수 있게 연결구조를 디자인하여 수십% 의 stain에도 각각의 전기특성이 유지되었다. 이처럼 스트레칭이 가능한 1차원 나노소재 소자는 그 유연성을 바탕으로 입는 옷처럼 구겨지거나 늘여지게 되는 다양한 스트레칭 상황에도 특성이 보장되어 미래 정보전자소자로 많은 응용이 가능할 것으로 예상된다.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.303-306
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• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.