• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• Journal of Power Electronics
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• v.14 no.5
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• pp.1057-1068
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• 2014

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.40-46
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• 2005

A process variation compensation method called 'regulated drain detection' is proposed. This paper also shows the how this newly invented method is applied to a typical differential PLL. The proposed RDD(regulated drain detection) and its PLL application has been designed and tested in a $0.18{\mu}m$ 1-poly 3-metal plain digital process so that its stable performance and higher yield can be proven. The implemented PLL aimed to the operation range of 80MHz - 240MHz and the total die size is only $0.18{\mu}m$ including the internal loop filter. The tracking jitter characteristics is measured to less than 150 peak-to-peak under l.8V supply rail.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1289-1301
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• 1997

In a SDH network, one of the most important issues is the realization of network synchronization. In this paper, we presented the relationship between parameters and control algorithm of DP-PLL for design in a SDH based time, SSM processing time, PJE counter and reference switching time, and analyzed phase transients for one node and mutiple nodes through our simulation results with a standard specification. We suggested suitable design method of SDH-DP-PLL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.851-856
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• 2006

This paper studies about design of a transceiver using a single PLL. The transceiver has bandwidth of $424.7\sim424.95MHz$ and the communication method used 21 channels 12.5 KHz channel bandwidth and FSK modulation/demodulation method. Also, we designed low power wireless transceiver for data transmission using a single PLL. Finally, the transceiver set achieves the following characteristics : 8.15dBm output power, 45.97dBc spurious property.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.185-186
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• 2015

This paper introduces general single PLL(Phase Locked Loop) algorithm and compares with proposed PLL method. The suggested PLL uses low pass filter to reduce high harmonics in real grid and uses feed forward method to compensate phase delay of the low pass filter.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.256-257
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• 2013

계통 연계형 시스템에서 왜곡된 입력전압에 대해서 기본파 전압의 크기, 주파수, 위상 등을 정확히 추종함으로써 계통과 시스템 간의 빠르고 정확한 동기화 과정은 매우 중요하다. 본 논문은 불평형 및 고조파를 포함한 3상 전압 조건에서 기본파 성분의 위상 추출을 위한 두 가지 기법인 Time Delay PLL과 MDSOGI PLL기법을 Matlab Simulink를 통해 모델링하고 비교 분석 하였다. 동기좌표계에서 발생되는 고조파 성분의 영향을 저감시키는 효과를 확인하고 그 특성을 비교하였다.

• Journal of Power Electronics
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• v.19 no.2
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• pp.509-518
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• 2019

A novel islanding detection method is proposed in this paper. It is based on a frequency drooping PLL, which was presented in a previous work. The cause of errors in the non-detection zone (NDZ) of conventional frequency disturbance islanding detection methods (IDM) is analyzed. A frequency drooping phase-locked-loop (FD-PLL) is introduced into a single-phase grid-connected inverter (SPGCI), which can guarantee that grid current is in phase with the grid voltage. A novel FD-PLL IDM is proposed by improving this PLL. In order to verify the performance of the proposed FD-PLL IDM, a full performance comparison between the proposed IDM and typical existing active frequency drift IDMs is carried out, which includes both dynamic performance and steady performance. With the same NDZ, the total harmonic distortion of the grid-current in the dynamic process and steady state is analyzed. The proposed FD-PLL IDM, regardless of the dynamic or steady process, has the best power quality. Experimental and simulation results verify that the proposed FD-PLL IDM has excellent performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.69-77
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• 2012

We propose a PLL-type position control method for step motors. Our control method considerably improves the instability problem at rapid acceleration or deceleration, which is a major problem of conventional open loop control methods. Moreover, our controller reduces the steady state position error to zero and guarantees lower vibration and acoustic noise at high speed. Also, our controller can produce more torque at high speed, and hence it can extend the controllable velocity range. To demonstrate the practical significance of our control method, we present some simulation results for a commercially available step motor using Simulink.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.103-105
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• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.