A Canonical Small-Signal Linearized Model and a Performance Evaluation of the SRF-PLL in Three Phase Grid Inverter System

Abstract

Phase-locked loops (PLL) based on the synchronous reference frame (SRF-PLL) have recently become the most widely-used for grid synchronization in three phase grid-connected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRF-PLL, a canonical small-signal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steady-state error have been investigated. Finally, a noise model of a SRF-PLL has been put forward to analyze the noise rejection ability by computing the SNR (signal-to-noise ratio) of a SRF-PLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRF-PLL, they are also suitable for analyzing other types of PLLs.

Ⅰ. INTRODUCTION

A grid-connected inverter perfectly matches the philosophy of a phase-locked loop (PLL), since it should operate in harmony with the utility voltage. It should phase-lock its internal oscillator to the positive sequence voltage at the fundamental frequency in three phase systems to produce an amplitude and phase-coherent utility voltage that is applied to control grid-connected inverters or micro-grid inverters, such as distributed generation and storage systems, flexible ac transmission systems (FACTS), power line conditioners and uninterruptible power supplies (UPS) [1], [2]. Regardless of the detection approach used, it should work as quickly and accurately as possible, even if the utility voltage is distorted and unbalanced.

There are three main detection approaches in the literature. They are the zero-cross phase detection method, the stationary reference frame phase detection method, and the synchronous reference frame phase detection method [3]. A conversional grid-connected inverter offers a low degree of control and is synchronized to the utility by detecting the zero-crossing of the utility voltage. This assumes that the magnitude of the utility is well known and that the frequency is kept constant. This technique suffers from some drawbacks, such as inaccuracy and the detection of multiple zero-crossings in the case of a distorted grid voltage. To overcome these drawbacks, some modified methods based on comparators circuits with dynamic hysteresis [4], curve-filters [5] or predictive digital filtering algorithms [6] have been proposed. Since these methods employ a comparator as phase detector (PD) for detecting changes in the polarity of the grid voltage, the phase sensitivity should be Ug/π for a single phase system, and 3Ug/π for three phase voltages, where Ug is the phase magnitude of the utility voltage. A PI controller is used as a loop filter. More importantly, it has a small-signal linearized model that is identical to that of the conventional SRF-PLL.

The most popular and essential technique is a three-phase locked loop based on the synchronous reference frame [7]. This is often referred as the conventional SRF-PLL [8]. Since a PLL contains a phase detector, it is a nonlinear system, which is difficult for one to predict the electrical properties. Based on the operational principle of the conventional SRF-PLL, a canonical small-signal linearized model has been developed in Section Ⅱ.

Based on this model, several significant specifications of the SRF-PLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth have been investigated in Section Ⅲ. Then, the steady-state errors under various operation conditions, such as phase step, frequency step, amplitude step, amplitude ramp and so on, have also been discussed. These various operation conditions correspond to some practical cases, such as the phase jump of the utility voltage, low-voltage ride-through, and micro-grid inverters working in the island condition by employing the frequency droop control.

In Section Ⅳ, a noise model of the SRF-PLL has been put forward to estimate its performance in the presence of noise. By applying the proposed noise model, the noise rejection ability by computing the SNR of the SRF-PLL has been investigated. Several simulation and experimental results have been provided to verify and validate the obtained conclusions.

Although the proposed model and analysis method comes from the SRF-PLL, they are also suitable for analyzing other types of PLLs.

 

Ⅱ. CONVENTIONAL SRF-PLL AND ITS SMALL–SIGNAL LINEARIZED MODEL

Fig. 1 shows the general structure of the conventional SRF-PLL. It can be seen that this structure needs a coordinate transformation form a,b,c→dq, and the lock is realized by setting the reference Uq* to zero. A regulator, usually a PI, is used to control this variable, and the output of this regulator is the grid frequency. After the integration of the grid frequency, the utility voltage angle is obtained, which is fed back into the αβ→dq transformation module to transform it into the synchronous rotating reference frame [8]. If the utility voltage is unbalanced, such as the presence of an asymmetrical fault or distortion, it contains a positive-sequence and negative-sequence as well as high order harmonics. It is well known that the fundamental component of the positive-sequence is uniquely useful and the other components will affect the performance of the SRF-PLL. Therefore, a noise source UN is added which represents all of the harmonics except for the fundamental component of the positive-sequence.

Fig. 1.General structure of conventional SRF-PLL.

If the utility voltage is balanced and non-distortion, the coordinate transformation form can be expressed as:

In the steady state, the input voltage of the PI controller, uq, is equal to zero, and Substituting this condition into Eq. (1) yields:

It can be observed from Eq. (2) that the d component represents the amplitude of the three phase voltage va, vb, and vc, and its phase angle can be detected by the output of the PLL, if the utility voltage is balanced and non-distortion.

A. Operational Principle of the SRF-PLL and the Proposed Small-Signal Linearized Model

The q component uq in Eq. (2) is used to form a PLL, referred as a simplified model of the SRF-PLL, as shown Fig. 2. It consists of phase detector (PD), a PI controller and VCO. The operational principle of the PLL is as follows: according to the phase difference the PD produces the voltage uq. It is sent to the PI controller to suppress its high-frequency component, thus a DC output voltage uf is developed. This voltage adjusts the frequency to tend toward the incoming frequency ω, where Until and uq=0, the PLL reaches the steady state and maintains the output frequency and phase angle.

Fig. 2.Simplified model of SRF-PLL.

It should be noted that the PD is a nonlinear device due to its sinusoidal function. However, if the phase error, θe is very small, less than π/6, the output of the PD can be approximated by:

where

Therefore, when the PLL is locked or tends to lock, a small-signal linearized model of the PD can be given by:

Thus, a small-signal linearized model of the SRF-PLL is proposed, as depicted in Fig. 3.

Fig. 3.Small-signal linearized model of SRF-PLL.

Based on the proposed small-signal linearized model of the SRF-PLL, some typical transfer functions of the SRF-PLL can be derived as follows.

The open-loop transfer function of the SRF-PLL is

The closed-loop transfer function of the SRF-PLL is

The input-to-error transfer function of the SRF-PLL is

The noise-to-error transfer function the SRF-PLL is

B. Stability Consideration

The open-loop transfer function, Eq. (5), can be rewritten as:

where

The substitution of s=jω into Eq. (9) yields the frequency repose. Fig. 4 illustrates a Bode plot of the magnitude frequency response of T(s).

Fig. 4.Magnitude frequency response of T(s).

In Fig. 4, let the crossover frequency fc be fz so that the phase margin is about 45 degrees. Using the identity fc=fz yields:

The substitution of U+=466.62 and fc=2.7kHz yields kp=28.277 and ki=3.73*103. The simulation results are demonstrated in Fig. 5. It can be seen that the crossover frequency is about 2.71kHz and that the phase margin is about 53 degree to ensure stability and a fast dynamic response.

Fig. 5.The simulation results of the frequency response T(s), the parameters are: U+=466.62, fc=2.7kHz, kp=28.277 and ki=3.73*103.

 

Ⅲ. PERFORMANCE ANALYSIS OF THE SRF-PLL

The performance of the SRF-PLL is estimated in this section, including the capture time, the capture range, and the steady-state error.

A. Capture Time of SRF-PLL

The normalized transfer function of (6) can be rewritten as:

where ωn2 = U+ki,

By ignoring the LHP (left half plane) zero in Eq. (11), it can be approximated by a standard second order transfer function

The dynamic analysis of a standard second-order system has been studied in many textbooks. The following approximated formulas are present in reference [9]. The settling time ts can be calculated by the formula in [10],

where τ = 1/ςωn.

It is noted that the settling time is usually called the capture time in a PLL.

According to the parameters ki=3.73×103 and kp=28.277 in Section Ⅱ, the damping factor, natural frequency and capture time can be calculated, yielding ωn=1.139×104rad/s, ς=0.5 and ts=0.8ms, respectively.

The bandwidth of the PLL is:

For ς = 0.7 , the ω-3dB is:

According to Eq. (12), Eq. (13) and Eq. (14), an important formula can be derived that the product of the capture time ts and the bandwidth ω-3dB is constant, and the value of the product is ω-3dBts ≈ 2.3 under the condition of ς=0.7 and a 1% steady-state error for the step response. In other words, the capture time ts is inversely proportional to the bandwidth ω-3dB.

Experimental results are shown in Fig. 6. In Fig. 6(a), CH1, CH2 and CH3 are the three-phase utility voltages, and CH4 is a control signal. The phase of the utility voltage jumps forward 180 degree while the control signal CH4 has a step change at a triggering time point. In Fig. 6(b), CH1 is the estimated output phase of the SRF-PLL, and CH2 is the control signal. The vicinity waveforms of Fig. 6(b) at the triggering time point are enlarged as illustrated in Fig. 6(c) to measure the capture time, ts≈1ms. The steady-state error θe is denoted by CH1 shown in Fig. 6(d).

Fig. 6.Experimental waveforms of SRF-PLL when phase jumps. (a) Three-phase utility voltage. (b) Estimated phase of SRF-PLL. (c) Enlarged waveform of (b), (d) steady-state error.

Note that the capture time displays a considerable error between the theoretical result ts=0.8ms from Eq. (12) and the experimental result ts=1ms. Therefore, the expression result from Eq. (12) should be taken only as a guide rather than precise formula. This formula provides a rough estimate of the time response of the system since the time taken by the coordinate transformation in the SRF-PLL and the influence of the ignored zero of Eq. (11) are not yet considered in this formula [11]. This should be checked, usually by simulation, in order to verify whether the time specification has been properly met or not.

B. Capture Range of SRF-PLL

Another significant parameter of the PLL, called the capture range ΔωH, is the frequency range at which a PLL is able to keep statically phase-locked. This parameter can be calculated by:

where F(0) is the DC gain of the controller in Fig. 3.

If a PI controller is selected, the capture range ΔωH is infinite because PI controller has an infinite DC gain. Therefore, the capture range ΔωH is only limited by the maximum value of the integrator output. An infinite capture rang implies that the PLL has no ability to reject any noise since it can lock all of the frequency signals. Therefore, a PI controller is not a good choice to suppress the noise present in a PLL.

C. Steady-state Error of the SRF-PLL

In this section it is investigated how the PLL responds under various conditions: phase step, frequency step, frequency ramp, and magnitude step as well as magnitude ramp.

In practice, when a PLL is used for synchronization with the grid voltage in a grid-connected inverter, and a set of micro-grid inverters working in the island condition by employing the frequency droop control strategy [12]. The phase step, frequency step and ramp of the PCC voltage are always encountered. Moreover, the magnitude step and ramp always occur when the inverter is controlled to ride through the grid fault [13].

1) Case 1, Steady-state error in the case of variations in the phase and frequency of utility voltage: By applying Eq. (7), the steady-state error of the SRF-PLL can be expressed as:

If a phase step is applied to the utility voltage as a reference signal, then θ(s)=1/s and:

This conclusion has already been proved in Fig. 6(d).

Similarly, since θ(s)=ω(s)/s, the steady state error formula of the frequency variation applied to a reference input gives:

If a frequency step of the utility voltage is used as an input, then ω(s)=1/s and:

If a frequency ramp of the utility voltage acts on the input, then ω(s)=1/s2 and:

The open-loop transfer function of (5) shows that this PLL is a type Ⅱ system, with two poles at the origin. This means that it is able to track the utility voltage phase step, frequency step and phase ramp (change slowly in a constant slop) without any steady-state errors.

Moreover, the normalized closed-loop transfer function from ω to shown in Fig. 3, can be written as:

Compared with the expression of Hθ, as shown in Eq. (11), a pole at the origin is added in Hω. A diagram of the poles and zeros location of the closed-loop transfer function Hω is illustrated in Fig. 7.

Fig. 7.Diagrams of the poles and zeros location of the closed-loop transfer function Hω .

As show in Fig. 7, the dominant pole is at the origin, rather than the pair of complex poles, p1 and p2. Thus, the system presents first-order system features so that its dynamic performance is not as good as the pervious closed system defined by Eq. (12). Experimental results are shown in Fig. 8. In Fig. 8(a), CH1, CH2 and CH3 are three-phase utility voltages, and CH4 is a control signal. A frequency jump of the utility voltage occurs from 50Hz to 60Hz, while the control signal of CH4 has a step change at a triggering time point. In Fig. 8(b), CH1 shows a steady-state error for the SRF-PLL. It can be observed that its steady-state error is zero, but the capture time ts is about 25ms.

Fig. 8.Experimental waveforms of SRF-PLL when frequency jumps. (a) Utility voltage. (b) Waveform of steady-state error.

In addition, a constant steady state error should exist in a conventional SRF-PLL when it is used in a set of micro-grid inverters working in the isolation island condition by adopting the frequency droop control strategy.

2) Case 2, steady-state error analysis of the magnitude variation of the utility voltage applied to an input signal: When the magnitude of the utility voltage fluctuates, and the phase is kept constant, the equivalent model is shown in Fig. 9. There are two parts in this model. One is the linear time-varying part, and the other is the linear time-invariant part. The system performance of the magnitude variation is analyzed in the Bode diagram shown in Fig. 10. The nonlinear system is analyzed by using the method of describing function.

Fig. 9.The equivalent model when the magnitude of the utility voltage fluctuates, and phase is kept constant.

Fig. 10.The Bode diagram when the amplitude of the utility voltage fluctuates.

When the magnitude of the utility voltage is normal, kt is equal to kt1. When the magnitude of the utility voltage drops at time=t2, the gain kt is equal to kt2, and the amplitude frequency response curve moves downward. However, the phase frequency response curve remains unchanged.

In summary, as shown in Fig. 10, when the magnitude of the utility voltage drops, the gain-crossover frequency and phase margin decrease, but the system remains stable for the PI controller. Variations in the magnitude have no effect on the steady-state error.

Experimental results are shown in Fig. 11 and Fig. 12. In Fig. 11(a), Ch1, Ch2 and CH3, are three-phase utility voltages, and CH4 is a control signal. The amplitude of the utility voltage drops from 466V to 233V while the control signal steps. As shown in Fig. 11(b), CH1 displays the steady-state error for the SRF-PLL, and CH2 is a control signal. It can be seen that the magnitude step has no effect on the steady-state error.

Fig. 11.Experimental waveforms of SRF-PLL when a amplitude step of the utility voltage is applied. (a) Utility voltage. (b) Waveform of steady-state error.

Fig. 12.Experimental waveforms of SRF-PLL a amplitude ramp of utility voltage is applied. (a) Utility voltage. (b) Waveform of steady-state error.

As shown in Fig. 12(a), the amplitude ramp of the utility voltage is applied, and Fig. 12(b) shows that the amplitude ramp has no effect on the steady-state error.

It can be seen from the above analysis that if the amplitude of the utility voltage fluctuates, the conventional SRF-PLL has no steady-state error. It only decreases the crossover frequency and phase margin of the system.

The performance of the conventional SRF-PLL has been summarized and listed in Table I.

TABLE ITHE PERFORMANCE OF CONVENTIONAL SRF-PLL

 

Ⅳ. PERFORMANCE IN THE PRESENCE OF NOISE

Noise is an extremely important issue when a PLL is employed to detect the fundamental component of the positive-sequence voltage in the control systems of grid-connected inverters or micro-grid inverters.

A. Noise Model of SRF-PLL

If the utility is unbalanced and its output voltage contains some high order harmonics, such as the 3rd, 5th, 7th…, then the voltage vector expression in the dq plane in Eq.(1) may be modified as follows:

The formula of (22) can be rewritten in the following compact form:

where

Assuming that the positive-sequence component is locked in the steady state, and then the formula of (22) becomes:

The first term of Eq. (24) is the fundamental component of the positive-voltage, the summation term is the high order harmonic components and the third is the negative-voltage component.

The q component of Eq. (24) can be expressed as:

Hence, the noise source is represented by UN, as illustrated in Fig. 1.

The small-signal linearized model of the SRF-PLL, shown in Fig. 3, can be modified to achieve the noise model of the SRF-PLL, shown in Fig. 13. Here, ko is the sensitivity of the voltage-controlled frequency oscillator (VCO), and it is equal to 1.

Fig. 13.Noise model of SRF-PLL.

B. Noise Performance

By applying the Mason formula to the block diagram of the noise model shown in Fig. 13, the input-to-output transfer function HN(s) is given by:

where

If a PI controller is used, and the parameters are: U+=466.62, kp=28.277 and ki=3.73*103, frequency response of HN(s) is depicted in Fig. 14.

Fig. 14.Frequency response of the noise transfer function HN(s), the parameters are: U+=466.62, fc=2.7kHz, kp=28.277 and ki=3.73*103.

The following conclusions can be drawn form Fig. 14. The frequency response of HN(s) exhibits a high-pass characteristic with a cutoff frequency The cutoff frequency fc is smaller than the grid frequency fo. In other words, according to Eq. (25), the all components of UN can pass through the controller directly without any attenuation and reach to the input terminal of the VCO. Therefore, the SRF-PLL does not have the ability to reject noise.

Usually, a low-pass filter is included in the loop to alleviate noise as shown in Fig. 15. Since 1/TL ≪ 2ω0 is satisfied, and the noise cannot reach the terminal of the VCO, the SRF-PLL has the ability to reject noise.

Fig. 15.Small-signal linearized model of SRF-PLL with low-pass filter.

The open-loop transfer function T(s) is modified as:

The zero of the PI controller ωz should be selected to be lower than ωp, and the amplitude frequency response of T(s) can be plotted, as shown in Fig. 16. The phase margin is determined by the middle-frequency-band of (ωp-ωz). Usually, let ωp/ωz ≈ 5-10 so that the phase margin is about 30-60 degrees, and the crossover frequency is equal to ωp/3.

Fig. 16.The bode diagram of the open-loop transfer function T(s) of SRF-PLL with low pass filter.

A low-pass filter is added into the loop to alleviate noise. However, the above analysis indicated that the crossover frequency is rather low, and the fast dynamic response is not satisfied.

Fig. 17 shows a simulation result using MATLAB with the following parameters: ωp =314rad/s, ωz = 40rad/s, and ωp/ωz= 7.8. The simulation result demonstrates that the crossover frequency is only 18Hz, and phase margin is about 50 degrees.

Fig. 17.Frequency response of the open-loop transfer function T(s) of SRF-PLL with low pass filter.

The experimental results are shown in Fig. 18. In Fig. 18(a), CH1, CH2 and CH3, are three-phase utility voltage, and CH4 is a control signal. A phase step of 180 degrees is applied, and a 3th harmonic component with a value of five percent is injected into the grid. As shown in Fig. 18(b), CH1 and CH2 represent the input and output signals of the low-pass filter. This shows that the harmonic component is eliminated with the low-pass filter, but the capture time ts is about 50ms. In sum, the ability to suppress noise and the dynamic response are mutually contradictory for the SRF-PLL.

Fig. 18.Experimental waveform of SRF-PLL with low pass filter when phase step of the three-phase voltage is applied. (a) Utility voltage. (b) Waveform of steady-state error.

C. SNR (signal-to-noise ratio) of the SRF-PLL

Based on the noise model of the SRF-PLL shown in Fig. 13 and Eq. (26), the input noise voltage of the VCO is given by:

Eq. (25) shows that the noise contains two parts: unbalance noise and high harmonic noise. For grid-connected inverters, unbalance noise is dominant. However, the high order harmonic noises should be considered for micro-grid inverters.

1) Case 1, SNR for unbalance noise: For grid-connected inverters, unbalanced noise is dominant. Therefore, Eq. (28) is employed to compute the unbalance noise response, such as:

It can be seen from Fig. 14 that the amplitude is 4.88dB, and the phase is 14 degree at f=100Hz. If the noise voltage is UN(t)=UNsin(2ωt), the input voltage of the VCO is:

The output of the VCO is a constant with value of 50Hz under ideal conditions. If the utility voltage is unbalanced, the output frequency of the VCO is given by:

Eq. (31) indicates that the output frequency of the PLL becomes a frequency modulation signal instead of a constant frequency, as shown in Fig. 19.

Fig. 19.Estimating frequency waveforms of the PLL by affecting the unbalance noise.

The signal-noise-ratio is defined as:

For example, when the parameters are: UN = 0.3U+, the SNR is only SNRUB = 2.14dB.

It is obvious that the SNR of the SRF-PLL is so low that the output frequency of the SRF-PLL is seriously distorted.

2) Case 2, SNR for high harmonic noise: The grid voltage may be distorted in the case of micro-grids working in the island condition or in weak grids with a high grid impedance because their gridvvoltage is prone to notable distorted by harmonics, switching notches and noise. Therefore, the high-order harmonic noise needs to be considered in this case.

If the noise voltage is defined as:

The voltage of the input terminal of the VCO is:

The output frequency of the VCO is given by:

The signal-noise-ratio is defined as:

Therefore, the output frequency of the PLL is 100π plus the even harmonic components if the utility voltage is distorted.

 

Ⅴ. CONCLUSIONS

It is difficult to investigate the electric characteristics of PLLs because they are nonlinear systems. This results from the coordinate transformation in the control block. In this paper, a canonical small–signal linearized model of the SRF-PLL has been developed to study the following issues: (1) the phase-locked process and operational principle; (2) the determination of the controller parameters; (3) the performance under various conditions.

By adopting the canonical small–signal linearized model, the following conclusions are obtained:

(1) The SRF-PLL with a PI controller is a normalized second-order system, and several formulas have been supplied in this paper to calculate its significant specifications such as the capture time, the capture rang, the bandwidth, the product of capture time and bandwidth as well as the parameters of the PI controller.

(2) It is revealed by analysis and experiment results that the steady-state error of the SRF-PLL is zero under the conditions of phase step, frequency step, amplitude step and ramp. However, the SRF-PLL has a constant error in case of a frequency ramp.

Noise analysis is also an extremely important issue for the PLL used in the control of grid-connected power inverters or macro grid inverters. In the performance analysis in the presence of noise, the following results and conclusions can be achieved:

(1) A noise model of the SRF-PLL has been proposed to investigate the performance of the SRF-PLL in the presence of noise.

(2) The SRF-PLL is incapable of rejecting noise. However, a low-pass filter in the loop can attenuate the noise at the cost of increasing the capture time.

(3)Two categories of the SNR have also been calculated.

In summary, this paper presents a detailed derivation of small-signal analysis methods to study the SRF-PLL. Valuable conclusion can be achieved with this method. These conclusions are verified and validated by simulation and experimental results.

Moreover, the conventional SRF-PLL can be commonly used as an essential block in some advanced PLLs, such as DDSRF-PLL [14], IPT-PLL [15], PQ-PLL [15], DSC-PLL [16], [17], DSOAF-PLL [18], FRF-PLL [19] and SSI-PLL [20]. They have a small-signal linearized model that is identical to that of the conventional SRF-PLL. As a result, the proposed model and analysis method are suitable for the other typical PLLs.