• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.76-84
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• 1999

For FH/SS communication, We discussed the method of indirect frequency synthesizer in several methods. The problem of sing1e frequency synthesizer using with PLL is a varied coefficient value of damping factor in frequency hopping time, which is caused unstable frequency. So. for stable frequency synthesizer, a coefficient of damping factor must be optimized and synthesized to be removed excessive response time. In this paper, we studied FH using with double loop frequency synthesizer which takes stable frequency. We made up a simulator and had a good performance(real time speed).

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.87-88
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• 2011

본 논문은 최근 빠른 속도로 성장하고 있는 신재생에너지 분야 중 태양광을 이용한 계통연계형 PV PCS의 PLL(Phase Locked Loop) 기법을 DSP로 처리할 수 있도록 디지털 논리회로로 구현하는 DPLL(Digital Phase Locked Loop) 기법을 제시하고 모델링과 시뮬레이션을 통하여 검증한다.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2350-2352
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• 2004

This paper presents the implementation-tation of the real-time software GPS Receiver based on FFT and FLL assisted PLL tracking algorithm. The FFT(fast fourier transform) based GPS si-gnal acquisition scheme provides a fast TTFF(time to first fix) performance. The tracking based on FLL assisted PLL enables tracking of GPS signal in a high dynamic environment. The designed software GPS receiver uses the indexing method for generating replica carrier to reduce computation load. The performance of the implemented GPS receiver is evaluated using high-dynamic simulated data from a simulator and real static data.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1064-1065
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• 2015

단상 계통 연계형 전력 변환기에서 계통과 연계하기 위해서는 계통의 위상 정보를 정확히 측정하여 전력 변환기의 출력 주파수와 위상이 동일한 상태로 전류가 공급 되도록 해야 한다. 본 논문에서는 단상 d-q 좌표 변환 기법을 통한 위상 동기화 기법을 적용하여 왜곡된 계통전압이 d축 전압에 야기 되는 에러 성분을 최소화 하는 보상 기법을 제안한다. 제안된 기법은 동기 d축 전압을 일정한 주기로 적분하여 에러 성분을 최소화 한 후, PI제어를 통해 d축 전압을 0으로 수렴하게 하는 기법이다. 제안된 기법은 추가적인 하드웨어를 요구하지 않는다. 본 논문의 타당성을 검증하기 위해 3[kW]급 단상 계통 연계형 전력변환기 시작품을 제작하고 실험을 통해 증명하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.197-200
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• 2001

Recently, Switching time is the principal factor in a design of frerquency synthesizer for Spread-Spectrum Communications. fast switching frequency synthesizer is important to improve the channel efficiency in a Frequency Hopping Spread Spectrum (FH-SS) tranceiver. In this paper, we design the frequency synthesizer with fast switching time as fast as 1${\mu}\textrm{s}$. In frequency synthesizer design, we use the interpolated PLL method inserted memory Look-up table of DDS to reduce switching time, and have result of improved channel efficiency about 20% by applying to FH-SS Transceiver.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.113-118
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• 2010

In This Paper, at the PSPICE model is presented by Piezoelectric Transformer and CCFL and equivalent circuit of fluorescent light. Highly effective fluorescent light release for next generation is developed for 35W supremacy model three wave length T5 fluorescent lamps. Lighting a candle experiment of T5 fluorescent lamps is carried out by employing Piezoelectric Transformer power-factor improvement circuit and inverter. PLL method is used for supplying a correct frequency of Piezoelectric Transformer operating.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.412-414
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• 1999

The FSK demodulation module is the circuit which detects the data being transmitted from reader by FSK method. It doesn't use the PLL, and has lower power consumption and easier integration than conventional FSK detector using the PLL. So in a smart card, it is suitable to apply. In this study, the FSK demodulation module of the low power smart card is designed and analyzed.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.72-73
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• 2013

본 논문은 계통 연계형 인버터에서 LPN 필터를 이용한 계통 위상 추종 방법을 제안한다. 기존의 FFT를 이용한 계통 위상 추종 알고리즘의 한주기 평균 계산부를 LPN 필터로 대체하여 위상 추종 성능을 개선하였다. 기존의 FFT-PLL의 경우 SRF-PLL과 달리 별도의 PI 게인 튜닝이 필요 없으며, 고조파와 같은 노이즈에 강인한 특징을 가진다. 하지만 위상 이동시에 새로운 위상을 추종하기 위해서 한주기 소요된다. 따라서 본 논문에서는 LPN 필터를 사용하여 반주기 이내에 추종할 수 있도록 성능을 개선하였다. 제안된 위상 추종 전략의 타당성을 실험을 통하여 검증하였다.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.170-183
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• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.