• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국전기전자재료학회논문지
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• 제14권11호
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• pp.869-873
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• 2001

The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

• 한국통신학회논문지
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• 제24권12A호
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• pp.2002-2007
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• 1999

본 논문에서는 유리기판 위에 고상결정화(SPC)로 제작된 n-채널 다결정 박막 트랜지스터(poly-Si TFT's)에 대해 전류-전압 특성, 이동도, 누설전류, 문턱전압, 그리고 부임계 기울기 등과 같은 전기적 특성을 측정함으로서 대면적, 고밀도 TFT-LCD에의 적용 가능성을 조사하였다. 채널 길이가 각각 2, 10, 25$\mu\textrm{m}$로 제작된 n-채널 poly-Si TFT에서, 전계 효과 이동도는 각각 11, 125, 116 $\textrm{cm}^2$/V-s이었으며, 누설전류는 각각 0.6, 0.1, 0.02 pA/$\mu\textrm{m}$로 나타났다. 또한 낮은 문턱전압과 q임계 기울기 그리고 양호한 ON-OFF ratio이 나타났다. 따라서, SPC로 제작된 poly-Si TFT는 대형유리기판에 디스플레이 패널과 구동시스템을 동시에 집적하는 대면적, 고밀도 TFT-LCD에 적용 가능한 것으로 판단된다.

• 전자공학회논문지D
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• 제35D권12호
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• pp.53-58
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• 1998

다결정 실리콘 박막 트랜지스터를 이용한 회로의 성능 향상을 위하여 새로운 구조의 4-terminal buried channel poly-Si TFT(BCTFT)를 설계하고 제작하였다. BCTFT는 moderate 도핑이 된 buried channel을 이용하므로 기존의 다결정 실리콘 TFT보다 ON-전류와 전계 효과 이동도가 n-형과 p-형 소자 각각 5배와 10배 향상되었다. BCTFT는 moderate 도핑된 buried 채널과 counter 도핑된 body 사이의 junction 공핍에 의하여 캐리어의 이동이 억제 되므로 OFF-전류가 증가하지 않았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.87-88
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• 2006

Recently, poly-Si TFT-LCD starts to be mass produced using excimer laser annealing (ELA) poly-Si. The main reason for this is the good quality poly-Si and large area uniformity. We report the influence of channel length and width on poly-Si TFTs performance. Transfer characteristics of p-channel poly-Si thin film transistors fabricated on polycrystalline silicon (poly-Si) thin film transistors (TFTs) with various channel lengths and widths of 2-30 ${\mu}m$ has been investigated. In this paper, we analyzed the data of p-type TFTs. We studied threshold voltage ($V_{TH}$), on/off current ratio ($I_{ON}/I_{OFF}$), saturation current ($I_{DSAT}$), and transconductance ($g_m$) of p-channel poly-Si thin film transistors with various channel lengths and widths.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.239-242
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• 2008

We have investigated the reliability of short channel ($L=1.5{\mu}m$) p-type ELA poly-Si TFTs under hot carrier stress. Threshold voltage of short channel TFT was significantly more shifted to positive direction than that of long channel TFT under the same stress. This result may be attributed to electron trapping at the interface between poly-Si film and gate oxide layer.