• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.147-156
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• 2005

CGI is a standard interface rule between web server and gateway devised for the gateway's standard output to replace a static web document in UNIX environment. So, it is common to use standard I/O statements provided by the programming language for the CGI gateway. But the standard I/O mechanism is one of buffer strategies that are designed transparently to operating system and optimized for generic cases. This means that it nay be useful to apply another optimization to the standard I/O environment in CGI gateway. In this paper, we introduced standard output method and file output method as the two output optimization areas for CGI gateways written in C language in the UNIX/LINUX systems, and applied the proposed methods of each area to Debian LINUX, IBM AIX, SUN Solaris, Digital UNIX respectively. Then we analyzed the effect of them focused on execution time. The results were different from operating system to operating system. Compared to normal situation, the best case of standard output area showed about $10{\%}$ improvement and the worst case showed $60{\%}$ degradation in file output area where some performance improvements were expected.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.4
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• pp.326-334
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• 1991

We propose an optical Asynchronous Transfer Mode(ATM) switching system using free-space optics and an output buffer memory. The distributor system in the switching fabric was analyzed using the Huygens-Fresnel principle and lens transformation. For monochromatic illumination, a pattern similar to the Fourier transform of the input distribution was observed across the output plane. A spatially broadened intensity distribution across the the output plane can be expected when the system is illminated with a partially coherent, quasimonochromatic beam. Spatially coherent pulses as short as 100fs can propagate through the distributor without severe spatial broadening.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.862-869
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• 2000

In a switch routing system, buffers are indispensible to prevent signal collision during routing process. For a photonic switching system, optical buffers are also indispensible if the system requires an active routing rather than a simple optical cross-connect(OXC). To cope with WDM technologies in optical comminication systems in these days, photonic switching system also has to deal with WDM signals. Therefore, optical buffers needed in a switching system has to be routed to the same output. For the receiver to recognize these signals separately, parallel WDM signals during rearrangement process. In this paper, we propose a novel all optical WDM output buffer whose structure, hardware, SNR and BER characteristics are improved a lot comparing with those of previously reported ones. From the analysis of the proposed buffer, the new buffer can hold 255 WDM cells keeping BER of 10-9 as long as a contrast ratio(gain on-off ratio) of optical gate(semiconductor optical amplifier) nside the buffer is 30dB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.243-246
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• 2002

This paper presents a study on the design and implementation of modulized I/O buffer control system for large capacity cable check. A 8bit I/O buffer basic module which has feedback loops with input and output buffers is simulated in PSpice and implemented with logic gates. This system is composed of 18 sub-boards which have 3 channels of 32bit data buses, and of a main board with MPC860 microprocessor.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.39-45
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• 2020

In the production process, the buffer acts as a buffer to alleviate some of the problems such as delays in delivery and process control failures in unexpected situations. Determining the optimal buffer size can contribute to system performance, such as increased output and resource utilization. However, there are difficulties in allocating the optimal buffer due to the complexity of the process or the increase in the number of variables. Therefore, the purpose of this research is proposing an optimal buffer allocation that maximizes throughput. First step is to design the production process to carry out the research. The second step is to maximize the throughput through the harmony search algorithm and to find the buffer capacity that minimizes the lead time. To verify the efficiency, comparing the ratio of the total increase in throughput to the total increase in buffer capacity.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• Journal of IKEEE
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• v.26 no.3
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• pp.462-467
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• 2022

The feedback buffer structure is proposed to alleviate the overshoot and undershoot phenomenon and the regulation of the output voltage. The conventional LDO regulator undergoes a regulation voltage change caused by a constant load current change. An LDO regulator with a feedback voltage sensing structure operates in the input voltage range of 3.3 to 4.5 V and has a load current of up to 150 mA at output voltage of 3 V. According to the simulation results, a regulation value of 6.2 mV was ensured when the load current uniformly changed to 150 mA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.743-746
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• 2005

This paper proposes a novel structure of output buffer circuits for PDP data drivers. The proposed circuit is free from capacitive coupling effect from the output electrode and suppresses the short circuit currents, which improves the current driving capability and reduces the power consumption.