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Design of the low noise CMOS LDO regulator for a low power capacitivesensor interface

저전력 용량성 센서 인터페이스를 위한 저잡음 CMOS LDO 레귤레이터 설계

  • Kwon, Bo-Min (Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University) ;
  • Jung, Jin-Woo (Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University) ;
  • Kim, Ji-Man (Department of Nano Engineering, Inje University) ;
  • Park, Yong-Su (Department of Electronics, Chung cheong University) ;
  • Song, Han-Jung (Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University)
  • 권보민 (인제대학교 나노시스템공학과) ;
  • 정진우 (인제대학교 나노시스템공학과) ;
  • 김지만 (인제대학교 나노공학부) ;
  • 박용수 (충청대학교 전기전자학부) ;
  • 송한정 (인제대학교 나노시스템공학과)
  • Published : 2010.01.30

Abstract

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

Keywords

References

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