• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.527-533
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• 1998

An optimized PWM switching strategy for an induction motor voltage control is developed and demonstrated. Space vector modulation in voltage source inverter offers improved DC-bus utilization and reduced commutation losses, and has been therefor recognizedas the perfered PWM method, especially in the case of digital implementation. Three-phase invertor voltage control by space vector modulation consists of switching between the two active and one zero voltage vector by using the proposed optimal PWM algorithm. The prefered switching sequence is defined as a function of the modulation index and period of a carrier wave. The sequence is selected by suing the inverter switching losses and the current ripple as the criteria. For low and medium power application, the experimental results indicate that good dynamic response and reduced harmonic distortion can be achieved by increasing switching frequency.

• Journal of information and communication convergence engineering
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• 제13권3호
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• 디지털산업정보학회논문지
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• 제15권4호
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제11권6호
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• pp.167-174
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• 2022

PIPO 경량 블록암호는 ICISC'20에서 발표된 암호이다. 본 논문에서는 32-bit RISC-V 프로세서 상에서 PIPO 경량 블록암호 ECB, CBC, CTR 운용 모드의 단일 블록 최적화 구현과 병렬 최적화 구현을 진행한다. 단일 블록 구현에서는 32-bit 레지스터 상에서 효율적인 8-bit 단위의 Rlayer 함수 구현을 제안한다. 병렬 구현에서는 병렬 구현을 위한 레지스터 내부 정렬을 진행하며, 서로 다른 4개의 블록이 하나의 레지스터 상에서 Rlayer 함수 연산을 진행하기 위한 방법에 대해 설명한다. 또한 CBC 운용모드의 병렬 구현에서는 암호화 과정에 병렬 구현 기법 적용이 어렵기 때문에 복호화 과정에서의 병렬 구현 기법 적용을 제안하며, CTR 운용모드의 병렬 구현에서는 확장된 초기화 벡터를 사용하여 레지스터 내부 정렬 생략 기법을 제안한다. 본 논문에서는 병렬 구현 기법이 여러 블록암호 운용모드에 적용 가능함을 보여준다. 결과적으로 ECB 운용모드에서 키 스케줄 과정을 포함하고 있는 기존 연구 구현의 성능 대비 단일 블록 구현에서는 1.7배, 병렬 구현에서는 1.89배의 성능 향상을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.65-68
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• 2000

In this paper, design parameters are investigated and design procedure is established for PCS mobile station, especially for receiver RF block. And simulation environment to analyze parameters of the receiver RF block to determine whether it satisfies the receiver standard, IS-98C, is calculated. Design parameters are simulated and optimized. With simulated results, PCS mobile station is implemented and tested. Measured results show good agreement with simulation Design procedure can be used to get optimum characteristics for each of receiver block. By using optimum characteristics, mobile station can be designed more efficiently.

• 대한의용생체공학회:의공학회지
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• 제9권2호
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• pp.239-246
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• 1988

This paper describes the design and implementation of personal computer assisted karyotyping system of Giemsa stained chromosomes. The system consists of an Image Acquisition Module being capable of $256 {\times} 256$ pixels and its relevent software modules optimized for karyotyping. The results of karyotyping using this system with an image of chromosomes taken from the Rana Amurensis are acceptable. As a result of this study we can save our load oweing to the conventional hand- karyotyping and the high-cost computer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.341-344
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• 2000

Several new via structures in printed circuit boards are proposed, fabricated and characterized in RF regime. The new structure with a larger inductance component in the bottom layer shows 3㏈ improvement over the conventional structure. The ADS simulation with model parameters extracted from 3D fie]d solver matches with the characterization of these vias

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.517-520
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• 2003

Orthogonal Frequency Division Multiplexing (OFDM) is a promising technology for high speed multimedia communication in a frequency selective multipath channel. In this paper, Software IPs for the synchronizer of IEEE 802.11a Wireless LAN system are designed and optimized for TI's TMS320C6201 fixed point DSP. As a result of the execution cycles of the target DSP for each functions of the system, an efficient HW/SW partitioning method can be considered.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2005년도 가을 학술발표논문집 Vol.32 No.2 (2)
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• pp.433-435
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• 2005

자바의 문제점은 실행속도의 저하이다. 바이트코드 최적화 방법을 사용하는 CTOC(Class To Optimized Classes)에서 중간코드로 사용하는 3-주소 코드를 스택-기반 코드로 코드 확장 기법으로 변환 시 불필요한 코드가 생성된다. 이러한 불필요한 코드를 제거하기 위한 정보를 필요로 한다. 필요한 정보를 얻기 위한 분석기로 CFG생성기를 설계 및 구현한다.

• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.205-208
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• 2005

This paper is about the hardware implementation of the Hash algorithm, HAS-160, which is widely used for Internet security and authentication. VHDL modeling was used for its realization and the operation speed has been increased by the optimized scheduling of the operations required for step operations.