• 한국통신학회논문지
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• 제37권6B호
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• pp.414-422
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• 2012

본 논문에서는 초경량 대칭키 암호화 기법인 HUMMINGBIRD2 알고리즘을 센서 모트상에서의 최적화 구현기법을 제시한다. 효율적인 구현을 위해 센서보드상에 제공되는 레지스터의 활용을 극대화하며 최적화된 주소접근 기법을 적용하여 암복호화에 소요되는 시간을 최소화하였다. 해당 대칭키 암호화 구현기법을 통해 자원 한정적인 센서 상에서의 안전하고 효율적인 보안 통신이 가능하도록 한다.

• 전기학회논문지P
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• 제60권4호
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• pp.257-261
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• 2011

In this paper, we research the OLSR(Optimized Link State Routing Protocol) of the mobile ad-hoc network protocols, and design the system implementation based on the Embedded Linux for the Ubiquitous Space construction. We prove the performance of proposed system in the various experiment environments through several scenarios which is about transmitting the image data on the mobile ad-hoc network environment.

• Journal of information and communication convergence engineering
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• 제14권3호
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• pp.177-183
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• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• 정보보호학회논문지
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• 제31권3호
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• pp.473-480
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• 2021

차세대 공개키 암호 고속 연산을 위해서는 목표로 하는 컴퓨터 프로세서의 구조를 활용하여 암호화 기본 연산을 최적화 구현하는 것이 중요하다. 본 논문에서는 RISC-V 프로세서 상에서 차세대 공개키 암호 고속 연산을 위해 핵심 곱셈기 연산을 최적화 구현하는 기법을 제안한다. 특히 RISC-V 프로세서의 기본 연산자를 열 기반 곱셈기 연산알고리즘에 맞추어 최적 구현해봄으로서 이전 연구와 비교 시 256-비트 곱셈의 경우 약 19% 그리고 512-비트 곱셈의 경우 약 8%의 성능 향상을 RISC-V 프로세서 상에서 달성하였다. 마지막으로 RISC-V 프로세서에서 추가적으로 제공되면 곱셈 연산 성능 향상에 도움이 될 수 있는 확장 명령어 셋에 대해서도 확인해 보도록 한다.

• 정보보호학회논문지
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• 제33권3호
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• pp.401-410
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• 2023

본 논문에서는 NIST LWC 최종후보 중 하나인 SPARKLE을 64-비트 ARMv8 프로세서 상에서 최적화하는 방안에 대해 제안한다. 제안 방법은 두 가지로서 ARM A64 명령어를 이용한 구현과 NEON ASIMD 명령어를 이용한 구현이다. A64 기반 제안구현은 ARMv8 상에서 가용한 레지스터를 효율적으로 사용할 수 있도록 레지스터 스케줄링을 수행하여 최적화한다. 최적화된 A64 기반 제안구현을 활용할 경우 Raspberry Pi 4B에서 C언어 참조구현보다 1.69~1.81배 빠른 속도를 얻을 수 있다. 두 번째로, ASIMD 기반 제안구현은 하나의 벡터명령어를 통해 3개 이상의 ARX-box를 병렬적으로 수행하도록 데이터를 병렬적으로 구성하여 최적화한다. 최적화된 ASIMD 기반 제안구현은 A64 기반 제안구현보다 일반적인 속도는 떨어지지만, SPARKLE256에서 SPARKLE512로 블록 크기가 증가할 때 A64 기반 제안구현에서는 속도가 2.1배 느려지는 것에 비해 ASIMD 기반제안구현에서는1.2배밖에 느려지지 않다는 장점이 있다. 따라서 기존 SPARKLE보다 더 큰 블록 크기를 갖는 SPARKLE 변형 블록 암호 또는 순열 설계 시 ASIMD 기반 제안구현이 더 효율적이므로 유용한 자료로써 활용 가능하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• 산업기술연구
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• 제29권A호
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• pp.95-100
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• 2009

In this paper, we implemented a speaker-independent speech recognizer using the TMS320F28335 DSP which is optimized for control applications. For this implementation, we used a small-sized commercial DSP module and developed a peripheral board including a codec, signal conditioning circuits and I/O interfaces. The speech signal digitized by the TLV320AIC23 codec is analyzed based on MFCC feature extraction methed and recognized using the continuous-density HMM. Thanks to the internal SRAM and flash memory on the TMS320F28335 DSP, we did not need any external memory devices. The internal flash memory contains ADPCM data for voice response as well as HMM data. Since the TMS320F28335 DSP is optimized for control applications, the recognizer may play a good role in the voice-activated control areas in aspect that it can integrate speech recognition capability and inherent control functions into the single DSP.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제13권4호
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• pp.324-335
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• 2013

This article presents the design, control, and implementation of a small quad-rotor system under the practical limitation of being cost effective for private use, such as in the cases of control education or hobbies involving radio-controlled systems. Several practical problems associated with implementing a small quad-rotor system had to be taken into account to satisfy this cost constraint. First, the size was reduced to attain better maneuverability. Second, the main control hardware was limited to an 8-bit processor such as an AVR to reduce cost. Third, the algorithms related to the control and sensing tasks were optimized to be within the computational capabilities of the available processor within one sampling time. A small quad-rotor system was ultimately implemented after satisfying all of the above practical limitations. Experimental studies were conducted to confirm the control performance and the operational abilities of the system.

• Journal of information and communication convergence engineering
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• 제11권1호
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• pp.12-16
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• 2013

Sensor network is one of the strongest technologies for various applications including home automation, surveillance system and monitoring system. To ensure secure and robust network communication between sensor nodes, plain-text should be encrypted using encryption methods. However due to their limited computation power and storage, it is difficult to implement public key cryptography, including elliptic curve cryptography, RSA and pairing cryptography, on sensor networks. However, recent works have shown the possibility that public key cryptography could be made available in a sensor network environment by introducing the efficient multi-precision multiplication method. The previous method suggested a broad rule of multiplication to enhance performance. However, various features of sensor motes have not been considered. For optimized implementation, unique features should be handled. In this paper, we propose a fully optimized multiplication method depending on a different specification for sensor motes. The method improves performance by using more efficient instructions and general purpose registers.