• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1113-1122
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• 2004

This paper is basically to achieve the high-availability and high-reliability of the control system from the implementation of the fault-tolerant system using the hot-standby sparing technique. To meet the objective, we design and implement a board with fault tolerance I/O bus to detect the fault. Warm-standby sparing technique is the fault tolerance technique usually used for switching control system in present. This technique can be easily implemented, but can not detect the fault quickly and can malfunction because of the hardware fault. The hot-standby sparing fault tolerant technique implemented in this paper is consists of dual processor modules and a I/O processor using fault tolerant I/O bus. The proposed method can find the faults as soon as possible, so it can prevent from wrong operation. Also it is possible to normal re-service due to the short recovering time. To implement the fault-tolerant dual system with fault detection be, two daughter, called FTMA and FTIA, boards designed and implemented are applied to the system. And we also simulated the proposed method to verify the high-availability and high-reliability of the control system using Markov process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.523-533
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• 2019

The convergence of engineering and IT technology has brought many changes to the industry as well as academic research. In particular, computer simulation technology has evolved to a level that can accurately simulate actual physical phenomena and analyze them in real time. In this paper, we describe the CFD technology, which is mainly used in industry, and the post processor that uses the augmented reality which is emerging as the post-processing. Research on the visualization of fluid simulation results using AR technology is actively being carried out. However, due to the large size of the result data, it is limited to researches that are published in a desktop environment. Therefore, it is limitation that needs to be reviewed in actual space. In this paper, we discuss how to solve these problems. We analyze the fluid analysis results in the post-processing, and then perform optimizing data (more than 70%)to support operation in the mobile environment. In the visualization, lightweight data is used to perform real-time tracking using cloud computing, The analysis result is matched to the screen and visualized. This allows the user to review and analyze the fluid analysis results in an efficient and immersive manner in the various spaces where the simulation is performed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.436-444
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• 2018

Currently, the new substation automation uses the international standard IEC 61850 communication protocol. KEPCO is also constructing a new substation based on IEC 61850 from 2013 through the pilot application and research and development starting from 2007. However, there are few cases where existing substations(Transformer, T/L GIS, D/L GIS, etc.) have been used, and RTU based substations operating systems have been changed to SA substations based on IEC 61850. Therefore, the introduction of IEC 61850 in existing substation facilities has the advantage of enhancing the substantiality of the substation by reusing existing facilities, improving the interoperability with the latest substations introduced, and converting existing substations into systems suitable for unmanned operation. In this paper, we introduce a case of changing the existing RTU based substation operation system to digital substation using IEC 61850 field information processor, Ethernet switch and SA operation system. Also, IEC 61850 client authentication program and Wireshark, which is a packet analysis tool, verify IEC 61850 conformance and its feasibility.

• Korean Journal of Remote Sensing
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• v.38 no.2
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• pp.167-177
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• 2022

In order to obtain satellite image products using the image transmitted to the ground station after capturing the satellite images, many image pre/post-processing steps are involved. During the pre/post-processing, when converting from level 1R images to level 1G images, geometric correction is essential. An interpolation method necessary for geometric correction is inevitably used, and the quality of the level 1G images is determined according to the accuracy of the interpolation method. Also, it is crucial to speed up the interpolation algorithm by the level processor. In this paper, we proposed a lightweight CNN-based interpolation method required for geometric correction when converting from level 1R to level 1G. The proposed method doubles the resolution of satellite images and constructs a deep learning network with a lightweight deep convolutional neural network for fast processing speed. In addition, a feature map fusion method capable of improving the image quality of multispectral (MS) bands using panchromatic (PAN) band information was proposed. The images obtained through the proposed interpolation method improved by about 0.4 dB for the PAN image and about 4.9 dB for the MS image in the quantitative peak signal-to-noise ratio (PSNR) index compared to the existing deep learning-based interpolation methods. In addition, it was confirmed that the time required to acquire an image that is twice the resolution of the 36,500×36,500 input image based on the PAN image size is improved by about 1.6 times compared to the existing deep learning-based interpolation method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.869-872
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• 2008

This paper presents the VHDL implementation procedure of the passive RFID tag in Ultra High Frequency RFID system. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation on prototyping board. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of the interrogation rate. Also with UART communication, verify a inventory Round in Gen2 Protocol. The verification results with the fastest data rate, 640kbps, and multi tags environment scenario show that the implemented tag spend 1.4ms transmitting the 96bits EPC to reader.