• 전자공학회논문지A
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• 제32A권12호
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• 전자공학회논문지C
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• 제34C권1호
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• 전기학회논문지P
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• 제53권1호
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• Journal of Power Electronics
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• 제16권3호
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• pp.1087-1096
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• 2016

This paper reports an investigation conducted on two diagnostic methods based on the switching voltage pattern of IGBT open-circuit faults in voltage-source inverters (VSIs). One method was based on the bridge arm pole voltage, and the other was based on bridge arm line voltage. With an additional simple circuit, these two diagnostic methods detected and effectively identified single and multiple open-circuit faults of inverter IGBTs. A comparison of the times for the diagnosis and anti-interference features between these two methods is presented. The diagnostic time of both methods was less than 280ns in the best case. The diagnostic time for the method based on the bridge arm pole voltage was less than that of the method based on the bridge arm line voltage and was 1/2 of the fundamental period in the worst case. An experimental study was carried out to show the effectiveness of and the differences between these two methods.

• The Journal of the Acoustical Society of Korea
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• 제14권2E호
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• pp.43-49
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• 1995

인공지능(AI)의 한기법인 Space Search 기법을 이용하여 회로의 단선 결함의 유무 및 결함위치를 찾아내는 방법을 제시하였다. 보통 회로의 결함은 단선 및 단락의 구조적 결함으로 나뉘어진다. 두가지 결함 모두 회로의 기능에 중대한 이상을 초래한다. 그중 단선에 의한 회로의 결함에 대하여 다루었다. 우선 회로를 net와 net의 연결 path에 따라 tree 구조로 변환하였다. 서로 독립된 net들은 서로 다른 tree의 node를 이루며 각각의 tree는 적기적으로 연결됨이 없다. 각 tree의 최상단부의 root node에 test vector를 입력하고 최하단부의 leaf node에서 vector를 관찰하여 입력된 test vector와 비교한다. 그 비교 결과 동일 유무에 따라 결함의 유무를 판정한다. 결함이 있다고 판정된 leaf node는 depth search 방법에 의하여 root node쪽으로 test vector를 관찰하여, 전기적 신호에 의하여 회로의 서놔 단선된 위치를 찾아내도록 하는 방법을 제시하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.36-37
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• 2016

The main cause of electrical fires are caused due to short circuit and open circuit. This is generates an instantaneous electric arc or spark accompanied with such electric faults. These arcs generate a pressed wire, contact badness, and a weakness in the wire coating etc.. This research proposes a protection circuit to prevent open-phase accident due to contact failure of electromagnetic contactor, tracking arc fault, open-phase within the three-phase electrical control panel which is the most commonly applied in the industry. The proposed circuit also alarms and cuts off of power system when electrical faults occurs. In addition, the proposed circuit is validated by various electric accident simulator.

• Journal of Power Electronics
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• 제12권1호
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• pp.208-214
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• 2012

This paper presents a novel approach based on the loci of instantaneous symmetrical components called "Wing Shape" which requires the measurement of three input stator currents and voltages to diagnose interturn insulation faults in three phase induction motors operating under different loading conditions. In this methodology, the effect of unbalanced supply conditions, constructional imbalances and measurement errors are also investigated. The sizes of the wings determine the loading on the motor and the travel of the wings while their areas determine the degree of severity of the faults. This approach is also applied to detect open circuit faults or single phasing conditions in induction motors. In order to validate this method, experimental results are presented for a 5 hp squirrel cage induction motor. The proposed technique helps improve the reliability, efficiency, and safety of the motor system and industrial plant. It also allows maintenance to be performed in a more efficient manner, since the course of action can be determined based on the type and severity of the fault.

• Journal of Power Electronics
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• 제16권4호
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• pp.1415-1425
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• 2016

This paper presents a new approach for fault diagnosis in three-level neutral point clamped inverters. The proposed method is based on the average values of the positive and negative parts of normalized output currents. This method is capable of detecting and locating multiple open-circuit faults in the controlled power switches of converters in half of a fundamental period of those currents. The implementation of this diagnostic approach only requires two output currents of the inverter. Therefore, no additional sensors are needed other than the ones already used by the control system of a drive based on this type of converter. Moreover, through the normalization of currents, the diagnosis is independent of the load level of the converter. The performance and effectiveness of the proposed diagnostic technique are validated by experimental results obtained under steady-state and transient conditions.

• 대한전자공학회논문지
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• 제27권11호
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• pp.42-48
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• 1990

본 논문에서는 CMOS 회로의 stuck-open 고장 검출을 위한 로브스트(robust)테스트 생성방법을 제안한다. CMOS 회로에 대한 입력 벡터들간의 비트(bit)위치와 해밍중(Hamming weight)의 관계를 고려하여 초기화 패턴을 구함으로써 stuck-open 고장검출을 위한 테스트 생성 시간을 감소시킬 수 있으며, 고장검출을 어렵게하게 하는 입력변이지연(input transition skew)의 문제를 해결하고, 테스트 사이퀸스의 수를 최소화시킨다. 또한 회로에 인가할 초기화 패턴과 테스트 패턴간의 해밍거리(hamming distance)를 고려하여 테스트 사이퀸스를 배열하므로써 테스트 사이퀸스의 수를 감소시킨다.

• 대한전자공학회논문지
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• 제21권6호
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• pp.78-84
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• 1984

CMOS 논리회로에서 부가회로없이 time skew와 무관하게 stuck-open(이하 s-op) 고장을 검출할 수 있는 새로운 알고리즘을 제안한다. 즉, CMOS회로 구성요소로서 Domino CMOS 이 회로를 채택하여 회로의 클럭킹 게이트를 하나의 branch로 간주 모델화하고, transition test를 이용하여 테스트 시이퀸스를 구한다. 또한 이 알고리즘을 VAXII/780상에서 임의의 CMOS회로에 적용시켜 보므로써, 종래의 방법에서 time skew로 인하여 검출될 수 없었던 모든 s-op 고장이 검출됨을 보였다.