• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.198-208
• /
• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.1
• /
• pp.1-11
• /
• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.53 no.1
• /
• pp.22-27
• /
• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.1087-1096
• /
• 2016

This paper reports an investigation conducted on two diagnostic methods based on the switching voltage pattern of IGBT open-circuit faults in voltage-source inverters (VSIs). One method was based on the bridge arm pole voltage, and the other was based on bridge arm line voltage. With an additional simple circuit, these two diagnostic methods detected and effectively identified single and multiple open-circuit faults of inverter IGBTs. A comparison of the times for the diagnosis and anti-interference features between these two methods is presented. The diagnostic time of both methods was less than 280ns in the best case. The diagnostic time for the method based on the bridge arm pole voltage was less than that of the method based on the bridge arm line voltage and was 1/2 of the fundamental period in the worst case. An experimental study was carried out to show the effectiveness of and the differences between these two methods.

• The Journal of the Acoustical Society of Korea
• /
• v.14 no.2E
• /
• pp.43-49
• /
• 1995

In this paper a space search technique is used to detect and locate the faults of the circuit interconnections. The circuit interconnections are represented by the tree structure and the tree space is searched to detect and locate the open faults of the circuit interconnections. The breadth search is used to detect the open faults and reduce the space size. The depth search is used to locate the open faults.

• Proceedings of the KIPE Conference
• /
• 2016.07a
• /
• pp.36-37
• /
• 2016

The main cause of electrical fires are caused due to short circuit and open circuit. This is generates an instantaneous electric arc or spark accompanied with such electric faults. These arcs generate a pressed wire, contact badness, and a weakness in the wire coating etc.. This research proposes a protection circuit to prevent open-phase accident due to contact failure of electromagnetic contactor, tracking arc fault, open-phase within the three-phase electrical control panel which is the most commonly applied in the industry. The proposed circuit also alarms and cuts off of power system when electrical faults occurs. In addition, the proposed circuit is validated by various electric accident simulator.

• Journal of Power Electronics
• /
• v.12 no.1
• /
• pp.208-214
• /
• 2012

This paper presents a novel approach based on the loci of instantaneous symmetrical components called "Wing Shape" which requires the measurement of three input stator currents and voltages to diagnose interturn insulation faults in three phase induction motors operating under different loading conditions. In this methodology, the effect of unbalanced supply conditions, constructional imbalances and measurement errors are also investigated. The sizes of the wings determine the loading on the motor and the travel of the wings while their areas determine the degree of severity of the faults. This approach is also applied to detect open circuit faults or single phasing conditions in induction motors. In order to validate this method, experimental results are presented for a 5 hp squirrel cage induction motor. The proposed technique helps improve the reliability, efficiency, and safety of the motor system and industrial plant. It also allows maintenance to be performed in a more efficient manner, since the course of action can be determined based on the type and severity of the fault.

• Journal of Power Electronics
• /
• v.16 no.4
• /
• pp.1415-1425
• /
• 2016

This paper presents a new approach for fault diagnosis in three-level neutral point clamped inverters. The proposed method is based on the average values of the positive and negative parts of normalized output currents. This method is capable of detecting and locating multiple open-circuit faults in the controlled power switches of converters in half of a fundamental period of those currents. The implementation of this diagnostic approach only requires two output currents of the inverter. Therefore, no additional sensors are needed other than the ones already used by the control system of a drive based on this type of converter. Moreover, through the normalization of currents, the diagnosis is independent of the load level of the converter. The performance and effectiveness of the proposed diagnostic technique are validated by experimental results obtained under steady-state and transient conditions.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.11
• /
• pp.42-48
• /
• 1990

In this paper robust test generation for stuck-open faults in CMOS circuits is proposed. By obtaining initialization patterns and test patterns using the relationship of bit position and Hamming weight among input vectors for CMOS circuit test generation time for stuck-open faults can be reduced, and the problem of input transition skew which make fault detection difficult is solved, and the number of test sequences are minimized. Also the number of test sequences is reduced by arranging test sequences using Hamming distance between initialization patterns and test patterns for circuit.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.6
• /
• pp.78-84
• /
• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.