• Journal of Information Processing Systems
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• 제8권2호
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• pp.241-262
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• 2012

An understanding of quality attributes is relevant for the software organization to deliver high software reliability. An empirical assessment of metrics to predict the quality attributes is essential in order to gain insight about the quality of software in the early phases of software development and to ensure corrective actions. In this paper, we predict a model to estimate fault proneness using Object Oriented CK metrics and QMOOD metrics. We apply one statistical method and six machine learning methods to predict the models. The proposed models are validated using dataset collected from Open Source software. The results are analyzed using Area Under the Curve (AUC) obtained from Receiver Operating Characteristics (ROC) analysis. The results show that the model predicted using the random forest and bagging methods outperformed all the other models. Hence, based on these results it is reasonable to claim that quality models have a significant relevance with Object Oriented metrics and that machine learning methods have a comparable performance with statistical methods.

• 대한자원환경지질학회:학술대회논문집
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• 대한자원환경지질학회 2003년도 춘계 학술발표회 논문집
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• pp.315-315
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• 2003

Gold mineralization at Kyaukpahto occurs as stockworks/disseminations and locally as breccia zones in silicified sandstones of Lower to Middle Eocene Male Formation of Myanmar. The mineralization is spatially related with NNE -trending fracture zones_probably tensional open fractures caused by the right-lateral Sagaing fault system. Intensive silicification, sericitization, argillic alteration, sulfidation, and decalcification are recognized in the Kyaukpahto mine area. (omitted)

• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.874-875
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• 2007

This paper introduces major potential faults of IPMSM and their simulation realization methods. The faults of IPMSM, generally, contain single-phase open circuit, single-phase or 3-phase short circuit, and uncontrolled generation. When different fault occurs, the circuit of total system including motor and inverter also will be changed. Therefore, it is necessary to analyze and establish independent model for each kind of fault. In this paper, first, the drive circuit is analyzed as different fault type. Then, the corresponding simulation results solved in Simulink@MATLAB are given. The absence of experiment results leads that the veracity of simulation results can not be verified, but the tendency will be explained by theory analysis.

• 전기학회논문지P
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• 제53권1호
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제16권4호
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• pp.238-245
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• 2016

Inverters are considered the basic building blocks of industrial electrical drive systems that are widely used for various applications; however, the failure of electronic switches mainly affects the constancy of these inverters. For safe and reliable operation of an electrical drive system, faults in power electronic switches must be detected by an efficient system that is capable of identifying the type of faults. In this paper, an open switch fault identification technique for a three-phase inverter is presented. Single, double, and triple switching faults can be diagnosed using this method. The detection mechanism is based on stator current analysis. Discrete wavelet transform (DWT) using Daubechies is performed on the Clarke transformed (-) stator current and features are extracted from the wavelets. An artificial neural network is then used for the detection and identification of faults. To prove the feasibility of this method, a Simulink model of the DWT-based feature extraction scheme using a neural network for the proposed fault detection system in a three-phase inverter with an induction motor is briefly discussed with simulation results. The simulation results show that the designed system can detect faults quite efficiently, with the ability to differentiate between single and multiple switching faults.

• 대한전자공학회논문지
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• 제27권11호
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• pp.42-48
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• 1990

본 논문에서는 CMOS 회로의 stuck-open 고장 검출을 위한 로브스트(robust)테스트 생성방법을 제안한다. CMOS 회로에 대한 입력 벡터들간의 비트(bit)위치와 해밍중(Hamming weight)의 관계를 고려하여 초기화 패턴을 구함으로써 stuck-open 고장검출을 위한 테스트 생성 시간을 감소시킬 수 있으며, 고장검출을 어렵게하게 하는 입력변이지연(input transition skew)의 문제를 해결하고, 테스트 사이퀸스의 수를 최소화시킨다. 또한 회로에 인가할 초기화 패턴과 테스트 패턴간의 해밍거리(hamming distance)를 고려하여 테스트 사이퀸스를 배열하므로써 테스트 사이퀸스의 수를 감소시킨다.

• 한국산학기술학회논문지
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• 제17권3호
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• pp.450-456
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• 2016

케이블에 인가되는 신호로 의사잡음 수열을 사용하여 인가신호와 반사신호의 시간 상관 분석을 실시하여 케이블 고장을 검출하는 STDR (sequence time domain reflectometry)은 노이즈 환경에 강하고, 단선, 합선을 포함한 간헐적 고장의 검출이 가능한 것으로 알려져 있다. 하지만 고장 위치의 거리가 멀거나 경미한 고장의 경우 반사신호의 감쇄가 크고 상관계수가 작아지게 되어, 케이블 고장 판별이 어렵거나 측정 거리 오차가 커진다. 또한 위상과 피크치 검출에 의한 고장 탐지 자동화가 어렵게 된다. 따라서 본 논문에서는 기존의 STDR의 고장 검출 성능을 향상시키기 위해 케이블에 인가되는 인가신호의 상관계수의 최댓값을 검출하고, 다음으로 인가신호를 제거하여 반사신호의 상관계수의 최댓값을 검출하는 알고리즘을 제안하였다. 제안된 방법은 저압 전력 케이블에서의 고장 검출 실험을 통해 성능을 입증하였다. 그 결과 제안된 방법은 신호가 감쇄되더라도 전통적인 STDR보다 고장 여부의 정확한 구분과 위치의 추적이 가능하였다. 또한 기준신호 제거와 상관계수의 정규화를 통해 위상과 최대값 검출 방법을 사용함으로써 자동 고장 판별과 거리 계산에 오류가 발생하지 않았다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.2044-2045
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• 2008

This paper was studied fault possibility of glass insulator through the proper vibration and field vibration comparison. The proper vibration of 1 cell glass insulator have many frequency band and high amplitude showed in high frequency than low frequency. The field signal amplitude of viaduct and open route were biggest moment pantograph of high-speed rail. From the FFT analysis of viaduct and open route, in the case of positive direction, the strut tube insulator effect by vertical vibration was big, the frequency was 82.5Hz and 105Hz, respectively. However, in the case of negative direction, the vibration did not cause big effect. In comparison with the proper vibration of glass insulator, the resonance was not observed.

• 한국지능시스템학회논문지
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• 제17권4호
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• pp.534-539
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• 2007

본 논문에서는 저압 배선 진단 시스템 개발을 위한 지능형 차단 시스템을 제안한다. 제안된 배선 진단 시스템은 TFDR(Time-Frequency Domain Reflectometry) 알고리즘을 통해 배선이 어떤 상태인지를 보여 주는 시스템이다. 그리고 제안된 진단 시스템으로부터 얻은 신호를 분석하여 이상 종류에 따라 분류하는 시스템을 통해 지능형 차단 시스템을 제안한다. 일반적으로, TFDR을 통해 알아 낼 수 있는 이상의 종류는 damage, open 그리고 short 이다. 각 상황에 대한 효율적인 분류를 위하여 IF-THEN 규칙에 기반 한 분류기가 사용된다. 기존 TFDR이 수행되었던 통신선 케이블의 실험 데이터에 기반 한 실험을 통해 본 제안 내용의 우수성을 보이게 된다.