• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1037-1043
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• 2020

This paper presents a new Physical Unclonable Function (PUF) security chip based on a low-cost, small-area, and low-power semiconductor process for IoT devices. The proposed security circuit has multiple challenge-to-response pairs (CRP) by adding the switching circuit to the cross-coupled path between two inverters of the SRAM structure and applying the challenge input. As a result, the proposed structure has multiple CRPs while maintaining the advantages of fast operating speed and small area per bit of the conventional SRAM based PUF security chip. In order to verify the performance, the proposed switched SRAM based PUF security chip with a core area of 0.095㎟ was implemented in a 180nm CMOS process. The measurement results of the implemented PUF show 4096-bit number of CRPs, intra-chip Hamming Distance (HD) of 0, and inter-chip HD of 0.4052.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.159-164
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• 2013

Recently the solution integrated of vision and motion controller which are important element in automatiomn system has been many developed. However typically such a solutions has a many case that integrated vision processing and motion control into network or organized two chip solution on one module. We implement one chip solution integrated into vision and motion controller using Zynq-7000 that is developed recently as extended processing platform. We also apply EtherCAT to motion control that is industrial Ethernet protocol which have compatibility for open standardization Ethernet in order to control of motion because EtherCAT has a secure to realtime control and can treat massive data.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.311-317
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• 2011

In this paper, we proposed realtime image enhancing method on the three noise types of input images, such as haze, low contrast and back light images. Some conventional de-hazing algorithms have good performance but need large memories and high computational burdens. We proposed the efficient algorithm which not only removes the haze but also reduces memory usage and computational complexity. We implemented the realtime system by using DM6446 DSP chip, and it showed the excellent result in these three problems; haze, low contrast and back light. We implemented the system with the processing speed at 15 frames/sec.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.10
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• pp.907-913
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• 2015

This work presents a method to predict the near magnetic field distribution on the digital switching circuit mounted on PCB using co-simulation of circuit and electromagnetic fields. The proposed method first obtains the normalized near field distribution by exciting the signal and power ports of the switching circuit using sinusoidal sources. Then the real near magnetic field distribution is determined by weighting the normalized field distribution using the current spectrum of the switching circuit. To confirm the proposed method, a switching IC with a ring oscillator and a output buffer is fabricated and measured in the form of chip-on-board. The surface magnetic field distribution is measured using a magnetic probe above the PCB and compared with the simulation results. Experimental results show the correspondence between simulation and measurement results within 10 dB up to fifth harmonics.

• Korean Journal of Optics and Photonics
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• v.32 no.5
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• pp.230-234
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• 2021

Relief of thermal stress has received great attention, to improve the beam quality and stability of high-power laser diodes. In this paper, we investigate a microtrench structure engraved around a laser-diode chip-on-submount (CoS) to relieve the thermal stress on a laser-diode bar (LD-bar), using the SolidWorks® software. First, we systematically analyze the thermal stress on the LD-bar CoS with a metal heat-sink holder, and then derive an optimal design for thermal stress relief according to the change in microtrench depth. The thermal stress of the front part of the LD-bar CoS, which is the main cause of the "smile effect", is reduced to about 1/5 of that without the microtrench structure, while maintaining the thermal resistance.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.255-258
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• 2009

최근 EDA 툴의 기술적인 향상과 반도체 공정의 발달로 IC 설계자들은 RISC 프로세서, DSP 프로세서, 메모리 등 많은 IP가 하나로 집적되는 SoC구조가 가능해졌다. 하지만 기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가진다. 이러한 문제점은 SoC 내부의 IP들이 많을수록 SoC 플랫폼의 전체 성능이 저하되어, CPU 자체의 속도보다는 효율적인 통신에 의해 성능이 좌우된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 성능을 향상시키기 위하여 크로스바 스위치버스 구조를 제안한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스 구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상됨을 확인하였다.

• Current Optics and Photonics
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• v.6 no.1
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• pp.15-22
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• 2022

This paper describes the construction of a phase shifter with low loss and small volume. To construct it, we use the two graphene layers that are separated by a hexagonal boron nitride (hBN) and embedded in a silicon waveguide. The refractive index of the waveguide is adjusted by applying a bias voltage to the graphene sheet to create an optical phase shift. This waveguide is a compact device that only has a radius of 5 ㎛. It has a phase shift of 6π. In addition, the extinction ratio (ER) is 11.6 dB and the insertion loss (IL) is 0.031 dB. Due to its unique characteristics, this device has great potential in silicon on-chip optical interconnection and all-optical multiple-input multiple-output processing.