• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.315-321
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• 2005

Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.67-71
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• 2000

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.195-202
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• 2003

In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.55-60
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• 2001

RF MEMS is an exciting emerging technology that has great potential to develop TOC (Transceiver-on-Chip). Applications of the RF MEMS to wireless communications systems are presented. The ability of the RF MEMS technology to enhance the performance and to reduce the size of passive components, in particular, switches, inductors, and tunable capacitors, is addressed. A number of potential wireless system opportunities for the TOC are awaiting the maturation of the RF MEMS technology.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.36-36
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• 2004