• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.31-40
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• 2005

In this study, we study measurement of wafer processing throughput and sequence simulation of single wafer type for wafer cleaning equipments that were used for etching, cleaning and polishing of wafer. Based on finite state machine, simulation model was built with identification of robot's status according to scheduling algorithm. Moreover, through performance of simulation as above, throughput per hour of cleaning equipment was measured. By the simulation method that are proposed in this paper, we could measure the wafer throughput per hour according to recipe and robot motion speed, and find optimal recipe and moving sequence of robot that maximize the throughput.

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.6
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• pp.146-151
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• 2011

Wax spin coating is a part of several wafer handling processes in the silicon wafer polishing station. It is important to ensure the wax layer free of contamination to achieve the high degree of planarization on wafers after wafer polishing. Three-dimensional air flow characteristics in a wax spin coater are numerically investigated using computational fluid dynamics techniques. When the bottom of the wax spin coater is closed, there exists a significant recirculation zone over the rotating ceramic block. This recirculation zone can be the source of wax layer contamination at any rotational speed and should be avoided to maintain high wafer polishing quality. Thus, four air suction ducts are installed at the bottom of the wax spin coater in order to control the air flow pattern over the ceramic block. Present computational results show that the air suction from the bottom is quite an effective method to remove or minimize the recirculation zone over the ceramic block and the wax coating layer.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.5 no.2
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• pp.130-140
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• 1993

Average particle deposition velocity toward a horizontal semiconductor wafer in vertical airflow is measured by a wafer surface scanner(PMS SAS-3600). Use of wafer surface scanner requires very short exposure time normally ranging from 10 to 30 minutes, and hence makes repetition of experiment much easier. Polystyrene latex (PSL) spheres of diameter between 0.2 and $1.0{\mu}m$ are used. The present range of particle sizes is very important in controlling particle deposition on a wafer surface in industrial applications. For the present experiment, convection, diffusion, and sedimentation comprise important agents for deposition mechanisms. To investigate confidence interval of experimental data, mean and standard deviation of average deposition velocities are obtained from more than ten data set for each PSL sphere size. It is found that the distribution of mean of average deposition velocities from the measurement agrees well with the predictions of Liu and Ahn(1987) and Emi et al.(1989).

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• Journal of the Korean Wood Science and Technology
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• v.15 no.1
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• pp.12-21
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• 1987

본질(本質) Cement board제조(製造)를 위하여 지금까지 톱밥, 목편(木片) 및 목수(木手)(excelsior)가 사용되어 왔으나, Wafer를 사용한 제품(製品)은 아직 개발(開發)되지 않고 있는 실정이다. 따라서, 본(本) 연구(硏究)는 Cement wafer board를 압력별(壓力別), Wafer 길이별(別), Cement와 목재(木材)의 배합비별(配合比別), Wafer 배열별(排列別)로 제조(製造)하여 그 영향인자(影響因子)를 조사(調査)하고 이에 따른 제품(製品)의 물리적(物理的), 기계적(機械的) 성질(性質)을 구명(究明)하고자 실시(實施)하였으며 다음과 같은 결론(結論)을 얻었다. 1. Cement Wafer board 제품(製品)의 적정압력(壓力)은 30kg/$cm^2$이었고, 30kg/$cm^2$ 이상(以上)의 압에서는 board의 기계적 성질에 나쁜 영향을 미쳤다. 2. Cement와 목재(木材)의 배합비(配合比)가 2.1을 넘을 경우에는 board의 성질에 나쁜 영향을 끼쳤다. 3. 한쪽 방향(方向)으로 Cement-Wafer가 배열된 조건에서 제조된 CWB가 최고의 곡강도(曲强度)를 나타내었다. 4. CWB의 곡강도(曲强度)는 다른 목질(木質) Cement board보다 높은 값을 나타내었으나 박리강도(剝離强度)에 있어서는 목편 Cement board보다 약간 낮은 값을 나타내었다. 5. CWB의 난연성(難燃性) 시험(試驗)은 난연3급(難燃3級)을 만족시켰다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.216-216
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• 2012

The purpose of this work is to investigate a back surface field (BSF) on variety wafer resistivity for industrial crystalline silicon solar cells. As pointed out in this manuscript, doping a crucible grown Cz Si ingot with Ga offers a sure way of eliminating the light induced degradation (LID) because the LID defect is composed of B and O complex. However, the low segregation coefficient of Ga in Si causes a much wider resistivity variation along the Ga doped Cz Si ingot. Because of the resistivity variation the Cz Si wafer from different locations has different performance as know. In the light of B doped wafer, we made wider resistivity in Si ingot; we investigated the how resistivities work on the solar cells performance as a BSF quality.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.