• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03a
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• pp.7-7
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• 2010

Energy harvesting from the environment has been of great interest as a standalone power source of wireless sensor nodes for Ubiquitous Sensor Networks(USN). In particular, the piezoelectric energy harvesting from ambient vibration sources has intensively researched because it has a relatively high power density comparing with other energy scavenging methods. Through recent advances in low power consumption RF transmitters and sensors, it is possible to adopt a micro-power energy harvesting system realized by MEMS technology for the system-on-chip. However, the MEMS energy harvesting system has some drawbacks such as a high natural frequency over 300 Hz and a small power generation due to a small dimension. To overcome these limitations, we devised a novel power generator with a spiral spring structure as shown in the figure. The natural frequency of a cantilever could be decreased to the usable frequency region (under 300 Hz) because the natural frequency depends on the length of a cantilever. In this study, the natural frequency of the energy harvester was a lower than a normal cantilever structure and sufficiently controllable in 50 - 200 Hz frequency region as adjusting weight of a proof mass. Moreover, the MEMS energy harvester had a high energy conversion efficiency using a shear mode ($d_{15}$) is much larger than a 33 mode ($d_{33}$) and the energy conversion efficiency is proportional to the piezoelectric constant (d). We expect the spiral type MEMS power generator would be a good candidate for a standalone power generator for USN.

• KSCI Review
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• v.14 no.1
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• pp.265-271
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• 2006

In this paper, we propose a new automatic fingerprint identification system that identifies individuals in large databases. The algorithm consists of three steps: preprocessing, classification, and matching, in the classification, we present a new classification technique based on the statistical approach for directional image distribution. In matching, we also describe improved minutiae candidate pair extraction algorithm that is faster and more accurate than existing algorithm. In matching stage, we extract fingerprint minutiaes from its thinned image for accuracy, and introduce matching process using minutiae linking information. Introduction of linking information into the minutiae matching process is a simple but accurate way, which solves the problem of reference minutiae pair selection in comparison stage of two fingerprints quickly. This algorithm is invariant to translation and rotation of fingerprint. The proposed system was tested on 1000 fingerprint images from the semiconductor chip style scanner. Experimental results reveal false acceptance rate is decreased and genuine acceptance rate is increased than existing method.

• Journal of Broadcast Engineering
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• v.25 no.2
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• pp.200-207
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• 2020

Recently, deep neural networks such as CNN are showing excellent performance in various fields such as image classification, object recognition, visual quality enhancement, etc. However, as the model size and computational complexity of deep learning models for most applications increases, it is hard to apply neural networks to IoT and mobile environments. Therefore, neural network compression algorithms for reducing the model size while keeping the performance have been being studied. In this paper, we apply few compression methods to CNN models and evaluate their performances in the embedded environment. For evaluate the performance, the classification performance and inference time of the original CNN models and the compressed CNN models on the image inputted by the camera are evaluated in the embedded board equipped with QCS605, which is a customized AI chip. In this paper, a few CNN models of MobileNetV2, ResNet50, and VGG-16 are compressed by applying the methods of pruning and matrix decomposition. The experimental results show that the compressed models give not only the model size reduction of 1.3~11.2 times at a classification performance loss of less than 2% compared to the original model, but also the inference time reduction of 1.2~2.21 times, and the memory reduction of 1.2~3.8 times in the embedded board.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.87-94
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• 2006

For realizing an ubiquitous home network(uHome-net), various sensors should be able to be connected to an integrated wire/wireless sensor network. This paper describes an application case of applying LonWorks technology being widely used in control network to wire/wireless sensor network in uHome-net and the design and application of LonRF device that consists of a neuron chip including LonTalk protocol, a 433.92MHz RF transceiver, a sensor, and application programs. As an application example of the LonRF device, the LonRF smart badge that can measure the 3D location of objects in indoor environment and interwork with the uHome-net was developed. LonRF device based home network services were realized on the uHome-net testbed such as indoor positioning service, remote surveillance service and remote metering service were realized. This research shows that LonWorks technology based sensor network could be applicable to the control network in an ubiquitous home network and the LonRF device can be used as a wireless node in various sensor networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.17-24
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• 2013

The localization accuracy in wireless sensor networks using ranging-based localization algorithms is greatly influenced by the ranging accuracy. Software implementation of HAL(Hardware Abstraction Layer) and MAC(Medium Access Layer) should seamlessly deliver the raw performance of ranging-based localization provided by hardware capability fully to the applications without degrading the raw performance. This paper presents the design and implementation of the software stack for IEEE 802.15.4a which supports normal ranging mode of the Nanotron's NA5TR1 RF chip. The experiment results shows that average ranging error rate with our implementation is 24.5% for the normal mode of the SDS-TWR ranging scheme.

• International Journal of Computer Science & Network Security
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• v.23 no.10
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• pp.147-156
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• 2023

Electronic voting machines (EVMs) are replacing research ballots due to the errors involved in the manual counting process and the lengthy time required to count the votes. Even though these digital recording electronic systems are advancements, they are vulnerable to tampering and electoral fraud. The suspected vulnerabilities in EVMs are the possibility of tampering with the EVM's memory chip or replacing it with a fake one, their simplicity, which allows them to be tampered with without requiring much skill, and the possibility of double voting. The vote data is shared among all network devices, and peer-to-peer verification is performed to ensure the vote data's authenticity. To successfully tamper with the system, all of the data stored in the nodes must be changed. This improves the proposed system's efficiency and dependability. Elections and voting are fundamental components of a democratic system. Various attempts have been made to make modern elections more flexible by utilizing digital technologies. The fundamental characteristics of free and fair elections are intractability, immutability, transparency, and the privacy of the actors involved. This corresponds to a few of the many characteristics of blockchain-like decentralized ownership, such as chain immutability, anonymity, and distributed ledger. This working research attempts to conduct a comparative analysis of various blockchain technologies in development and propose a 'Blockchain-based Electronic Voting System' solution by weighing these technologies based on the need for the proposed solution. The primary goal of this research is to present a robust blockchain-based election mechanism that is not only reliable but also adaptable to current needs.

• Journal of Internet Computing and Services
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• v.9 no.6
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• pp.1-13
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• 2008

Trusted Computing is a hardware-based technology that aims to guarantee security for machines beyond their users' control by providing security on computing hardware and software. TPM(Trusted Platform Module), the trusted platform specified by the Trusted Computing Group, acts as the roots for the trusted data storage and the trusted reporting of platform configuration. Data sealing encrypts secret data with a key and the platform's configuration at the time of encryption. In contrast to the traditional data sealing based on binary hash values of the platform configuration, a new approach called property-based data sealing was recently suggested. In this paper, we propose and analyze a new property-based data sealing protocol using the weakest precondition concept by Dijkstra. The proposed protocol resolves the problem of system updates by allowing sealed data to be unsealed at any configuration providing the required property. It assumes practically implementable trusted third parties only and protects platform's privacy when communicating. We demonstrate the proposed protocol's operability with any TPM chip by implementing and running the protocol on a software TPM emulator by Strasser. The proposed scheme can be deployed in PDAs and smart phones over wireless mobile networks as well as desktop PCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.52-59
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• 2007

In this paper, we analyzed and measured implant isolation characteristics for a 1.25 Gbps monolithic integrated hi-directional (M-BiDi) optoelectronic system-on-a-chip, which is a key component to constitute gigabit passive optical networks (PONs) for a fiber-to-the-home (FTTH). Also, we derived an equivalent circuit of the implant structure under various DC bias conditions. The 1.25 Gbps M-BiDi transmit-receive SoC consists of a laser diode with a monitor photodiode as a transmitter and a digital photodiode as a digital data receiver on the same InP wafer According to IEEE 802.3ah and ITU-T G.983.3 standards, a receiver sensitivity of the digital receiver has to satisfy under -24 dBm @ BER=10-12. Therefore, the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysed and measured results of the implant structure, the M-BiDi SoC with the implant area of 20 mm width and more than 200 mm distance between the laser diode and monitor photodiode, and between the monitor photodiode and digital photodiode, satisfies the electrical crosstalk level. These implant characteristics can be used for the design and fabrication of an optoelectronic SoC design, and expended to a mixed-mode SoC field.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.