• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.60-62
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• 2006

This paper presents an efficient frequency offset (FO) estimation algorithm for the orthogonal frequency division multiplexing (OFDM) based wireless local area networks (WLANS). The packet preamble imformation is utilized on the high rate WLAN standards adopted by the IEEE 802.11a. We present FO estimation schemes using diversity. In the simulation results, we prove that the presented schemes can improve the estimation performance compared with the convolutional scheme.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.319-320
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• 2008

In this paper, we propose a new frequency offset estimation algorithm for DBO-CSS which is a standard for wireless personal area network (WPAN). In DBO-CSS, there can be several integer multiples of $2{\pi}$ in the phase rotation caused by the frequency offset because of the long time difference between the samples of differential relation and the high permissible frequency offset of the crystal oscillators between the transmitter and the receiver. In this paper, we propose an estimation algorithm by using the relationships of each sub-chirp signals to find the integer part without phase ambiguity.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.125-130
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• 2013

Compared to OWR (One-Way Ranging) method that requires precise network time synchronization, TWR (Two-Way Ranging) method has advantages in building an indoor WPAN (Wireless Personal Area Network) location system with lower cost. However, clock offsets of nodes in WPAN system should be eliminated or compensated to improve location accuracy of the TWR method. Because conventional clock offset elimination methods requires multiple TWR transactions to reduce clock offset, they produce network traffic burden instead. This paper presents a clock offset estimation method that can reduce clock offset error with a single TWR transaction. After relative clock offsets of sensor nodes are estimated, clock offsets of mobile tags are estimated using a single TWR communication. Simulation results show that location accuracy of the proposed method is almost similar to the conventional clock offset elimination method, while its network traffic is about a half of the conventional method.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.5
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• pp.121-127
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• 2021

Reverse offset printing is considering as an emerging technology for printed electronics owing to its environmentally friendliness and cost-effectiveness. In reverse offset printing, selecting the materials for cliché and blanket is critical because of its minimum resolution, registration errors, aspect ratio of reliefs, pattern area, and reusability. Various materials such as silicon, quartz, glass, electroplated nickel plates, and imprinted polymers on rigid substrates can be used for the reverse offset printing of cliché. However, when new structures are designed for specific applications, new clichés need to re-fabricated each time employing multiple time-consuming and costly processes. Therefore, by modifying the blanket materials containing the printing ink, several new structures can be easily created using the same cliché. In this study, we investigated various elastomeric materials and evaluated their applicability for designing a highly stretchable blanket with controlled elastic deformation to implement tunable reverse offset printing.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.483-484
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• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.123-127
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• 2020

In this paper, the estimation of the disparity for depth extraction in monochrome complementary metal-oxide-semiconductor (CMOS) image sensors with offset pixel apertures is presented. To obtain the depth information, the disparity information between two different channel data of the offset pixel apertures is required. The disparity is caused by the difference in the response angle between the left- and right-offset pixel aperture images. A depth map is implemented by the generated disparity. Therefore, the disparity is the most important factor for realizing 3D images from the designed CMOS image sensor with offset pixel apertures. The disparity is influenced by the pixel height and offset value of the offset pixel aperture. To confirm this correlation, the offset value is set to maximum within the pixel area, and the disparity values corresponding to the difference in the heights are calculated and compared. The disparity is derived using the camera-lens formula. Two monochrome CMOS image sensors with offset pixel apertures are used in the disparity estimation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5A
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• pp.290-297
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• 2012

In this paper, we proposed new modulation schemes, Offset Phase Rotation Shift Keying (OPRSK) and Phase Shift Rotation Shift Keying (PSRSK), for medical in-body wireless body area network (WBAN) systems. In IEEE, the WBAN system is assigned as 802.15. Task Group (TG) 6, and the related standardization is being progressed. Recently, in this Group, Phase Silence Shift Keying (PSSK), Phase Silence Position Keying (PSPK) and Phase Rotation Shift Keying (PRSK), which can obtain higher power efficiency, are proposed as new modulation schemes for low-power operation of WBAN system. However, they have a disadvantage for non-linear amplifier distortion. Therefore, in this paper, we proposed OPRSK and PSRSK, which are robust to non-linear amplification, by employing a phase offset in constellation and a power distribution in symbol duration, and verified that the proposed methods have good perfomance and stable operation through performance evaluation.