• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.555-557
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• 2006

This paper represent improved On-line Turn off Angle control schemes for switched reluctance motors based on current control. For the purpose of the finding optimal commutation switching angle point, it is utilized him on and turn off position calculation with inductance vs. current vs. flux linkage analysis method. The goal of proposed paper is the maximization of the energy conversion per stroke and maximizing efficiency and obtaining approximately flat-topped current waveform. The proposed control scheme is demonstrated on a prototype experimental system.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권3호
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• pp.397-403
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• 2012

This paper describes a control method of turn-on/off angles to improve the efficiency of the switched reluctance generator(SRG) with a power closed-loop control system, and the inner-loop of the system is current hysteresis control. The SRG control system is constituted by the PI power controller and the two-level current hysteresis controller. By measuring and analyzing the system losses of different reference powers, speeds and turn-on/off angles, selection strategy of optimal turn-on/off angles is discussed. The proposed method is simple, reliable, and easy to achieve.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.240-242
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• 2013

In this paper, novel Carbon Nanotube Gate-Elongated Tunneling Field Transistor(CNT G-E TFET) is proposed. This proposed device is designed to decrease off-current around 2~6 orders of magnitude compared to the gate-channel size matched TFET. Mechanism of CNT G-E TFET creates additional steps in energy band structure so that off-current can be reduced. Since CNT TFETs show a great probability for tunneling processes and they are beneficial for the overall device performance in terms of switching speed and power consumption, CNT G-E TFET looks pretty much promising.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• 전력전자학회논문지
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• 제3권3호
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• pp.222-230
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• 1998

본 논문에서는 스너버 회로를 사용하지 않고 턴-온시 역회복 전류의 영향과 턴-오프 시 구동되는 IGBT에 발생하는 과전압을 제한할 수 있는 새로운 IGBT 게이트 구동회로를 제안한다. 제안하는 턴-온 게이트 구동기법은 턴-온 지연 시간을 증가시키지 않고 게이트-에이터 전압이 문턱전압 이상이 되면 IGBT의 입력 커패시턴스를 증가시킴으로써 게이트-에이터 전압의 증가율을 감소시키는 특징을 갖는다. 제안하는 턴-오프 게이트 구동기법은 전류의 크기에 따라 과전압을 제한하여 단락사고와 같은 대전류가 흐르는 경우 더욱 효과적으로 과전압을 제한하는 특징을 가진다. 또한, 여러 가지 조건에서 실험을 수행하여 제안한 IGBT 게이트 구동회로의 타당성을 검증한다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권3호
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• pp.99-104
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• 2002

lateral insulated gate bipolar transistors(LIGBTs) are extensively used in high voltage power IC application due to their low forward voltage drops. One of the main disadvantages of the LIGBT is its scow switching speed when compared to the LDMOSFET. And the LIGBT with reverse channel structure is lower current capability than the conventional LIGBT at the forward conduction mode. In this paper, the LIGBT which included p+ ring and p-channel gate is presented at the reverie channel structure. The presented LIGBT structure is proposed to suppress the latch up, efficiently and to improve the turn off time. It is shown to improve the current capability too. It is verified 2-D simulator, MEDICI. It is shown that the latch up current of new LIGBT is 10 times than that of the conventional LIGBT Additionally, it is shown that the turn off characteristics of the proposed LIGBT is i times than that of the conventional LIGBT. It is net presented the tail current of turn off characteristics at the proposed structure. And the presented LIGBT is not n+ buffer layer because it includes p channel gate and p+ ring.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1025-1028
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• 2005

Microcrystalline Si (${\mu}c-Si$) TFTs were fabricated using a conventional bottom gate amorphous Si (a-Si) process. A unique ${\mu}c-Si$ deposition technique and TFT architecture was proposed to enhance the reliability of the TFTs. This three-mask TFT fabrication process is comparable with existing a-Si TFT procesess. In order to suppress nucleation at the bottom interface of Si, before deposition of the ${\mu}c-Si$ an $N_2$ plasma passivation was conducted. A typical transfer characteristic of the TFTs shows a low off-current with a value of less than 1 pA and a sub threshold slop of 0.7 V/dec. The DC stress was applied to verify the use of ${\mu}c-Si$ TFTs for AMOLED displays. After 10,000 s of application of the stress, the off-current was even lowered and sub-threshold slope variation was less than 5%. For AMOLED displays, OLED pixel simulation was performed. A pixel current of 13 ${\mu}A$ was achieved with $V_{data}$ of 10 V. After the simulation, a linear equation for the pixel current was suggested.

• 한국해양학회지
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• 제21권3호
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• pp.136-145
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• 1986

Kim and Han이 1972년 발표한, 한국남동해안 연안해저표면퇴적물 21점에서 살아있는 개체와 죽은 개체를 합한 저서유공충 전체군집 자료를 기초로 하여 Dice 相以係數를 구하여 非加重雙群方法(Unweighted Pair Group Method)으로 군집분석 (Cluster analysis)해서 生物場(Biotope)을 구했다. 결과는 남쪽상과 북쪽상으로 대별되며, 남쪽상은 固有相과 깊은상, 북쪽상은 沿岸相과 固有相으로세분된다. 생물장들은 연구지역에서 우세한 해류와 연관이 있어서 남쪽고유상은 對馬暖流의 영향이 뚜렷하며, 남쪽 깊은상은 남하하는 底層冷水의 영향을 받았다. 북쪽연안상은 北韓寒流의 영향이 뚜렷하며, 북쪽고유상은 북한한류와 일부 東海固有水의 영향이 있다. 위의 현상은 인구지역의 상반부에는 北上하는 東韓暖流보다 남하하는 北韓 寒流가, 바깥쪽에서는 東海固有水가 큰 영향을 미치며,이는 난류가 연구지역의 오른쪽 지역의 표면을 따라 북상하기 때문인 것으로 믿어진다.

• 대한전자공학회논문지SD
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• 제46권4호
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• pp.21-27
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• 2009

본 연구에서는 고온에서 Schottky barrier SOI nMOS 및 pMOS의 전류-전압 특성을 분석하기 위해서 Er 실리사이드를 갖는 SB-SOI nMOSFET와 Pt 실리사이드를 갖는 SB-SOI pMOSFET를 제작하였다. 게이트 전압에 따른 SB-SOI nMOS 및 pMOS의 주된 전류 전도 메카니즘을 온도에 따른 드레인 전류 측정 결과를 이용하여 설명하였다. 낮은 게이트 전압에서는 온도에 따라 열전자 방출 및 터널링 전류가 증가하므로 드레인 전류가 증가하고 높은 게이트 전압에서는 드리프트 전류가 감소하여 드레인 전류가 감소하였다. 고온에서 ON 전류가 증가하지만 드레인으로부터 채널영역으로의 터널링 전류 증가로 OFF 전류가 더 많이 증가하게 되므로 ON/OFF 전류비는 감소함을 알 수 있었다. 그리고 SOI 소자나 bulk MOSFET 소자에 비해 SB-SOI nMOS 및 pMOS의 온도에 따른 문턱전압 변화는 작았고 subthreshold swing은 증가하였다.