• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2015년도 춘계학술발표대회
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• pp.61-63
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• 2015

본 논문에서는 애플리케이션 실행에 필요한 파일들을 검출하고, 그 파일들을 저 용량의 비 휘발성 메모리에 옮겨 시작 시간을 단축시킨다. 또한 각각의 파일들은 전체가 필요하지 않고 파일 중 일부분만 필요하기 때문에, 필요한 부분만 주 메모리에 선 적재 함으로써 시작 시간을 크게 개선하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Bulletin of the Korean Chemical Society
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• 제32권3호
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• pp.783-784
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• 2011

• 한국컴퓨터정보학회논문지
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• 제17권11호
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• pp.101-105
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• 2012

최근 스마트폰의 급격한 보급으로 개인정보 침해사고 및 프라이버시 침해를 통한 여러 가지 사회문제가 급속도로 증가하고 있으며, 이에 따라 개인 정보보호를 위한 다양한 연구 및 기술 개발이 이루어지고 있다. 개인의 모든 정보가 거의 들어 있다고 해도 과언이 아닌 스마트폰의 정보유출은 우리의 일상에서 쉽고 빈번하게 발생할 수 있는데, 포렌식 분석 툴을 이용하여 증거를 수집하거나 분석하기란 쉽지 않은 일이다. 현재 안드로이드 포렌식 연구는 비휘발성 메모리로부터 데이터를 수집하여 분석하는 기법에 집중되어 왔으며, 휘발성 데이터에 대한 연구는 미미한 실정이다. 안드로이드 로그는 휘발성 저장매체로부터 수집될 수 있는 휘발성 데이터이다. 안드로이드 로그는 안드로이드 시스템에서부터 애플리케이션에 이르기까지 최근의 모든 구동내역과 관련한 기록이 로그로 저장되기 때문에 안드로이드폰 사용을 추적할 수 있는 자료로 활용이 충분하다. 본 논문에서는 포렌식 분석 툴을 이용하지 않고 로그를 필터링하여 개인의 정보 유출 유무를 판단하여 대응할 수 있는 방법을 제시한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제16권2호
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• pp.207-211
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• 2010

스토리지 클래스 메모리 (SCM)는 비휘발성 속성과 바이트 단위의 임의 접근이 가능한 속성을 동시에 보유하고 있는 차세대 메모리 기술로써 그 활용 방안에 있어서 귀추가 주목된다. 기존 시스템에 SCM을 도입하면 시스템의 수행 속도와 안전성을 크게 향상할 수 있을 뿐만 아니라 기존의 시스템에서는 불가능했던 새로운 특징들을 제공할 수 있다. 본 연구는 혁신적인 용도로의 SCM 활용 가능성에 주목하며, 그 일환으로 SCM을 메인 메모리로 활용하여 종료 상태의 시스템에 전원이 인가되는 즉시 종전의 시스템 상태로 되돌아갈 수 있는 SOONN을 제안한다. 본 논문에서는 실제 임베디드 시스템 환경에서 프로토타입 시스템을 개발함으로써 SOONN의 실현 가능성을 제시한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.440-440
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• 2011

We report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C-V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ${\pm}3$ V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as $1{\times}105$. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above $1.5{\times}105$ cycles and a high ON/OFF ratio of ~105 could be achieved consistently even after quite a long retention time of more than $1{\times}106$ s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.186-189
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• 2002

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.17-21
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• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.