• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.85-91
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• 2012

In this paper, the large data processing and suitable FAT32 file system for industrial system using a PLC and CF memory was implemented. Most of PLC can't save the large data in user data memory. So it's required to the external devices of CF memory or NAND flash memory. The CF memory is used in order to save the large data of PLC system. The file system using the CF memory is NTFS, FAT, and FAT32 system to configure in various ways. Typically, the file system which is widely used in industrial data storage has been implemented as modified FAT32. The conventional FAT 32 file system was not possible for multiple writing and high speed data accessing. The proposed file system was implemented by the large data processing module can be handled that the files are copied at the 40 bytes for 1msec speed logging and creating 8 files at the same time. In a sudden power failure, high reliability was obtained that the problem was solved using a power fail monitor and the non-volatile random-access memory (NVSRAM). The implemented large data processing system was applied the modified file system as FAT32 and the good performance and high reliability was showed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.3
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• pp.200-205
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• 2000

This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

• Journal of KIISE
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• v.42 no.2
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• pp.183-189
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• 2015

Recently, computer systems have encountered difficulties in making further progress due to the technical limitations of DRAM based main memory technologies. This has motivated the development of next generation memory technologies that have high density and non-volatility. However, these new memory technologies also have their own intrinsic limitations, making it difficult for them to currently be used as main memory. In order to overcome these problems, we propose a hybrid main memory system, namely HyMN, which utilizes the merits of next generation memory technologies by combining two types of memory: Write-Affable RAM(WAM) and Read-Affable RAM(ReAM). In so doing, we analyze the appropriate WAM size for HyMN, at which we can avoid the performance degradation. Further, we show that the execution time performance of HyMN, which provides an additional benefit of durability against unexpected blackouts, is almost comparable to legacy DRAM systems under normal operations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.476-484
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• 2015

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

• KIISE Transactions on Computing Practices
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• v.24 no.3
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• pp.129-137
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• 2018

NVMe(Non-Volatile Memory Express) SSD(Solid State Drive) is a high-performance storage that makes use of flash memory as a storage cell, PCIe as an interface and NVMe as a protocol on the interface. It supports multiple I/O queues which makes it feasible to process parallel-I/Os on multi-core environments and to provide higher bandwidth than SATA SSDs. Hence, NVMe SSD is considered as a next generation-storage for data-center and cloud computing system. However, in the virtualization system, the performance of NVMe SSD is not fully utilized due to the bottleneck of the software I/O stack. Especially, when it uses I/O stack of the hypervisor or the host operating system like Xen and KVM, I/O performance degrades seriously due to doubled-I/O stack between host and virtual machine. In this paper, we propose a new I/O engine, called Direct-AIO (Direct-Asynchronous I/O) engine, that can access NVMe SSD directly for I/O performance improvements on QEMU emulator. We develop our proposed I/O engine and analyze I/O performance differences between the existed I/O engine and Direct-AIO engine.

• Journal of the Korean Magnetics Society
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• v.18 no.3
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• pp.103-108
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• 2008

Magnetoresistive random access memory (MRAM) don't get very public face on the field of non-volatile memory. Because recording capacity of MRAM is smaller than other non-volatile memory and structurally, magnetic efficiency of MRAM is very bad. We diminish a size of one cell in order to make MRAM of high recording capacity. But It don't make high recording field in general structures consisting of two current wire. Accordingly, We make a cell of small size is impossible. In this paper, we suggest new MRAM that it have two pole of high permeability on both ends of recording layer. Because magnetic efficiency of new MRAM is higher than exiting MRAM, it can make high recording field. And we can diminish the size of one cell due to recording layer of high coercivity. We used three-dimension finite element method to prove the reliability.

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.4
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• pp.607-614
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• 2011

This paper describes the development of pulse code modulation(PCM) data recorder with design, implementation and environmental test. PCM serial data that diverged from telemetry encoder output is used as the input and is reformed to parallel signal through FPGA processing. Controllers construct the packet by the sector and record it into non-volatile memory. Compact flash(CF) memory for data storage media, USB interface for data downloading, and a software for operating status diagnosis and file format conversion are used.