한국전기전자재료학회논문지 (Journal of the Korean Institute of Electrical and Electronic Material Engineers)

  • 제22권5호
  • /
  • Pages.386-389
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  • 2009
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  • 1226-7945(pISSN)
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  • 2288-3258(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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비휘발성 메모리를 위한 SiO2와 Si3N4가 대칭적으로 적층된 터널링 절연막의 전기적 특성과 열처리를 통한 특성 개선효과

Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO2 and Si3N4 Layers by Annealing Processes for Non-volatile Memory Applications

  • 김민수 (광운대학교 전자재료공학과) ;
  • 정명호 (광운대학교 전자재료공학과) ;
  • 김관수 (광운대학교 전자재료공학과) ;
  • 박군호 (광운대학교 전자재료공학과) ;
  • 정종완 (세종대학교 나노신소재공학부) ;
  • 정홍배 (광운대학교 전자재료공학과) ;
  • 이영희 (광운대학교 전자재료공학과) ;
  • 조원주 (광운대학교 전자재료공학과)
  • 발행 : 2009.05.01
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초록

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

키워드

참고문헌

  1. S. Lai, 'Tunnel oxide and $ETOX^{TM}$ flash scaling limitation', Int'l Non-Volatile Memory Technology Conf, p. 6, 1998
  2. K. Licharev, 'Layered tunnel barriers for non-volatile memory devices', Appl. Phys. Lett., Vol. 72, No. 15, p. 2137, 1998
  3. A. Korotkov, 'Resonant fowler-nordheim tunnelling through layered tunnel barriers', IEDM Tech. Dig., p. 223, 1999
  4. B. Govoreanu. P. Blomme, M. Rosmeulen, J. V. Houdt, and K. D. Meyer, 'VARIOT: A novel mulilevel tunnel barrier concept for low-voltage non-volatile memory devices', IEEE Electron Device Lett., Vol. 24, No. 2, p. 99, 2003 https://doi.org/10.1109/LED.2002.807694
  5. J. W. Jung and W. J. Cho, 'Tunnel barrier engineering for non-volatile memory', Journal of Semiconductor Technology and Science, Vol. 8, No. 1, p. 32, 2008 https://doi.org/10.5573/JSTS.2008.8.1.032
  6. J. Buckley, B. D. Salvo, G. Ghibaudo, M. Gely, J. F. Damlencourt, F. Martin, G. Nicotra, and S. Deleonibus, 'Investigation of $SiO_2/HfO_2$ gate stacks for application to non-volatile memory devices', Solid-State Electron., Vol. 49, p. 1833, 2005 https://doi.org/10.1016/j.sse.2005.10.005
  7. G. D. Wilk, R. M. Wallance, and J. M. Anthony, 'High-k gate dielectrics: Current status and materials properties consider- ations', J. Appl. Phys., Vol. 89, p. 5243, 2001 https://doi.org/10.1063/1.1361065
  8. Y. S. Lo, K. C. Liu, J. Y. Wu, C. H. Hou, and T. B. Wu, 'Band-gap engineering of tunnel oxide with multistacked layers of $Al_2O_3/HfO_2/SiO_2$ for Au-nanocrystal memory application', Appl. Phys. Lett., Vol. 93, p. 132907, 2008 https://doi.org/10.1063/1.2995862
  9. Y. Liu, S. Dey, S. Tang, D. Q. Kelly, J. Sarkar, and S. K. Banerjee, 'Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier', IEEE Trans. Electron. Diveces, Vol. 53, p. 2598, 2006 https://doi.org/10.1109/TED.2006.882395
  10. B. Bhushan and S. P. Murarka, 'Stress in silicon dioxide films deposited using chemical vapor deposition techniques and the effect of annealing on these stresses', J. Vac. Sci. Technol. B., Vol. 8, No. 5, p. 1068, 1990 https://doi.org/10.1116/1.584918
  11. D. A. Neamen, 'Semiconductor Physics and Device: Basic Principles, Trd Edition', McGraw Hill, p. 450, 2002