• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.963-968
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• 2013

Ionizing Radiation effects on MOS devices provide useful information regarding the behavior of MOS based devices and circuits in the electronic instrumentation parts and instructive data for making the high sensitive sensors. The study presents the results of the analysis on the structural characteristics of MOS capacitor for sensing the ionizing radiation effect. We performed numerical modeling of Ionizing-radiation effect on MOS capacitor and simulation using Matlab program. Also we produced MOS capacitors and obtained useful data through radiation experiment to analyse the characteristic of ionizing radiation effect on MOS capacitor. Increasing the thickness of MOS capacitor's oxide layer enhanced the sensitivity of MOS capacitor under irradiation condition, but the sensitivity of irradiated MOS capacitor is uninfluenced by the area of MOS capacitor. The high frequency capacitance of the MOS capacitor is found to be strongly affected by incident ionizing radiation.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1181-1182
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• 2008

The study presents the results of the analysis on the structural characteristics of MOS capacitor for sensing the ionizing radiation effect. Increasing the thickness of MOS capacitor's oxide layer enhanced the sensitivity of MOS capacitor under irradiation condition, but the sensitivity of irradiated MOS capacitor is uninfluenced by the area of MOS capacitor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.123-127
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• 1992

When MOS devices is exposed to radiation, radiation effects of P-type MOS capacitor can cause modulation and/or degradation in devices characteristics and its operating life. The oxide layer is grown in $O_2$+T.C.E. and its thickness ranges from 40 to 80 nm. Irradiations on MOS capacitor were performed by Cobalt-60 gamma ray source and total dose ranges from $10^4$ to $10^8$ rads. The radiation effect on electrical conduction characteristics(I-V) in MOS capacitor was measured as a function of gate oxide thickness and total dose. From the experimental result, I-V characteristics is found to be influenced strongly by total dose in irradiated p-type MOS capacitors. The ohmic current is dependant on of total dose in irradiated P-type MOS capacitors. This results are explained using surface states at interface radiation-induced traps.

• Asian-Australasian Journal of Animal Sciences
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• v.20 no.7
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• pp.1084-1091
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• 2007

Different levels of dietary mannanoligosaccharide (Bio-MOS, Alltech Inc.) were evaluated for their efficacy on performance and gut development of broiler chickens during a 6-week experimental period. Experimental diets contained (g MOS/kg diet) a low (0.5 g during the entire period), medium (1 g during the entire period), high (2 g during the entire period), or step down (2 g in the first week; 1 g in the second and third week; 0.5 g in the last three weeks) level of MOS. Control diets included a negative and a positive control (zinc bacitracin, ZnB, 50 ppm and 30 ppm in the first and last three weeks, respectively). MOS supplementation improved the growth performance of young birds and the effects became less when the birds got older. The growth response of birds was more obvious at the high dosage level of MOS treatment than the other MOS treatments and the growth performance of birds fed on the high MOS diet was comparable to that of birds fed on the ZnB diet. Depending on the dosage level and the age of birds, MOS seemed to reduce the size of the liver and the relative length of the small intestine but did not affect the relative weight of the other visceral organs (proventriculus, gizzard, pancreas, bursa and spleen) and that of the small intestine. A numerical increase in the small intestine digestibility of nutrients was noticed in the young birds fed on the MOS diet(s), but not in the older ones. Medium and/or high MOS treatment also increased the villus height of the small intestine of birds at different ages. Similar results were observed on the ZnB treatment. However, MOS and ZnB affected caecal VFA profile in different ways. MOS increased, or tended to increase, whereas ZnB reduced individual VFA concentrations in the caeca.

• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.207-210
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• 1996

This paper describes the analysis of the operation of the switched snubber in order to depress the surge voltage in the MOS-FET inverter. In this paper, the N-channel MOS-FET which operates faster than the P-channel MOS-FET was used for the inverter circuit. So, the inverter and switched snubber can operate at high-frequency in the order of MHz. The cause of generating the surge voltage in the high frequency inverter has been cleared, and then how to depress the surge voltage using the switched snubber consisting of an N-channel MOS-FET has been given. Furthermore, described is the power loss within the switched snubber which is made of an N-channel MOS-FET. The inverter having the N-channel MOS-FET used as a switched snubber can drive such a low impedance load such as mega-sonic transducer for a mega-sonic studied cleaner sufficiently.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.231-233
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• 1991

This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.