JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Efficient Management of PCM-based Swap Systems with a Small Page Size

  • Received : 2015.04.16
  • Accepted : 2015.06.08
  • Published : 2015.10.30
Download PDF
⟨ Previous Next ⟩

Abstract

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

Keywords

References

  1. M. Qureshi, V. Srinivasan, and J. Rivers, "Scalable high performance main memory system using phase-change memory technology," Proc. IEEE ISCA Conf., pp. 24-33, 2009.
  2. E. Lee, H. Bahn, and S.H. Noh, "Unioning of the buffer cache and journaling layers with non-volatile memory," Proc. USENIX FAST Conf., pp. 73-80, 2013.
  3. J. Mogul, E. Argollo, M. Shah, and P. Faraboschi, "Operating system support for NVM+DRAM hybrid main memory," Proc. USENIX HotOS Workshop, 2009.
  4. S. Lee, H. Bahn, and S. H. Noh, "CLOCK-DWF: a write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures," IEEE Trans. Comput., vol. 63, no. 9, pp. 2187-2200, 2014. https://doi.org/10.1109/TC.2013.98
  5. G. Dhiman, R. Ayoub, and T. Rosing, "PDRAM: a hybrid PRAM and DRAM main memory system," Proc. ACM/IEEE Design Automation Conf., pp.664-559, 2009.
  6. Phase Change Memory Product, http://www.micron.com/products/phase-change-memory, Micron, 2013.
  7. F.J. Corbato, "A paging experiment with the multics system," In Honor of P.M. Morse, MIT Press, 1969.
  8. B. Nale, R. Ramanujan, M. Swaminathan, and T. Thomas, "Memory channel that supports near memory and far memory access," PCT/US2011/054421, 2013.
  9. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," Proc. IEEE ISCA Conf., pp.14-23, 2009.
  10. N. Seong, D. Woo, and H. Lee, "Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping," Proc. IEEE ISCA Conf., pp. 383-394, 2010.
  11. B. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable DRAM alternative," Proc. IEEE ISCA Conf., pp. 2-13, 2009.
  12. B. Yang, J. Lee, J. Kim, J. Cho, S. Lee, and B. Yu, "A low power phase-change random access memory using a data-comparison write scheme," Proc. IEEE Symp. Circuit and Syst., 2007.
  13. S. Cho and H. Lee, "Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance," Proc. IEEE Symp. Microarchitect., 2009.
  14. B.Wongchaowart, M. Iskander, and S. Cho, "A content-aware block placement algorithm for reducing PRAM storage bit writes," Proc. IEEE MSST Conf., pp.1-11, 2010.
  15. M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Mosse, "Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems," ACM Trans. Architect. Code Optimization, vol. 8, no. 4, 2012.
  16. H. Seok, Y. Park, K. Park, and K. Park, "Efficient page caching algorithm with prediction and migration for a hybrid main memory," Applied Comput. Review, vol. 11, no. 4, 2011.
  17. M. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, "Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling," Proc. IEEE Symp. Microarchit., pp. 14-23, 2009.
  18. E. Lee, J. Jang, T. Kim, and H. Bahn, "On-demand snapshot: an efficient versioning file system for phase-change memory," IEEE Trans. Knowledge & Data Engineering, vol. 25, no. 12, pp.2841-2853, 2013. https://doi.org/10.1109/TKDE.2013.35
  19. E. Lee, S. Yoo, and H. Bahn, "Design and implementation of a journaling file system for phase-change memory," IEEE Trans. Comput., vol. 64, no. 5, pp. 1349-1360, 2015. https://doi.org/10.1109/TC.2014.2329674
  20. R. Ramanujan, R. Agarwal, and G. Hinton, "Apparatus and method for implementing a multilevel memory hierarchy having different operating modes," US 20130268728 A1, Intel Corporation, 2013.
  21. J. Condit, E. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee, "Better I/O through byte-addressable, persistent memory," Proc. ACM SOSP Conf., 2009.
  22. R. L. Coulson, "Co-optimizing systems, OS, applications, SSDs and NVM," Proc. Non-Volatile Memories Workshop, 2012.
  23. Valgrind, http://valgrind.org/
  24. H. Yoon et al., "Techniques for data mapping and buffering to exploit asymmetry in MLC PCM," SAFARI Technical Report No. 2013-002, 2013.