• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.161-172
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• 2021

Neuromorphic architecture is drawing attention as a next-generation computing that supports artificial intelligence technology with low energy. However, FPGA embedded boards based on Neuromorphic architecturehave limited resources due to size and power. In this paper, we compared and evaluated the image reduction method using the interpolation method that rescales the size without considering the feature points and the DCT (Discrete Cosine Transform) method that preserves the feature points as much as possible based on energy. The scaled images were compared and analyzed for accuracy through CNN (Convolutional Neural Networks) in a PC environment and in the Nengo framework of an FPGA embedded board.. As a result of the experiment, DCT based classification showed about 1.9% higher performance than that of interpolation representation in both CNN and FPGA nengo environments. Based on the experimental results, when the DCT method is used in a limited resource environment such as an embedded board, a lot of resources are allocated to the expression of neurons used for classification, and the recognition rate is expected to increase.

• Smart Media Journal
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• v.12 no.4
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• pp.19-26
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• 2023

IoT edge services utilizing neuromorphic hardware architectures are suitable for autonomous IoT applications as they perform intelligent processing on the device itself. However, spiking neural networks applied to neuromorphic hardware are difficult for IoT developers to comprehend due to their complex structures and various hyper-parameters. In this paper, we propose a method for generating spiking neural network (SNN) models that satisfy user performance requirements while considering the constraints of neuromorphic hardware. Our proposed method utilizes previously trained models from pre-processed data to find optimal SNN model parameters from profiling data. Comparing our method to a naive search method, both methods satisfy user requirements, but our proposed method shows better performance in terms of runtime. Additionally, even if the constraints of new hardware are not clearly known, the proposed method can provide high scalability by utilizing the profiled data of the hardware.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.64-67
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• 2018

A new CMOS neuron circuit for implementing bistable synapses with spike-timing-dependent plasticity (STDP) properties has been proposed. In neuromorphic systems using STDP properties, the short-term dynamics of the synaptic efficacies are governed by the relative timing of the pre- and post-synaptic spikes, and the efficacies tend asymptotically to either a potentiated state or to a depressed one on long time scales. The proposed circuit consists of a negative shifter, a current starved inverter and a schmitt trigger designed using 0.18um CMOS technology. The simulation result shows that the proposed circuit can reduce the total size of neurons, and the spike energy of the proposed circuit is much less compared to the conventional circuits.

• Ceramist
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• v.22 no.1
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• pp.17-26
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• 2019

The metal-to-insulator transition (MIT) with external stimuli is one of the main issues in correlated oxides. The physical properties are extremely sensitive to band filling, because the MIT is attributed to the strong correlation between electrons in narrow d-band. Since hydrogen is the smallest and lightest element, it is not only likely to doped reversibly in oxides, but also acts as a dopant to provide electrons. The correlated oxides showing MIT are structurally expanded after hydrogenation, and their electrical properties are drastically changed. Researches on this phenomenon have been actively carried out to date. They are of great scientific importance, and the use of this material is very diverse, including the development of next-generation hydrogen sensor, or hydrogen-based neuromorphic devices.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.166-171
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• 2023

This paper presents the synaptic characteristics of IGZO memristors in neuromorphic computing, using MATLAB/Simulink and NeuroSim. In order to investigate the variations in the conductivity of IGZO memristor and the corresponding changes in the hidden layer, simulations are conducted by using the MNIST dataset. It was observed from simulation results that the recognition accuracy could be dependent on various parameters of IGZO memristor, along with the experimental exploration. Moreover, we identified optimal parameters to achieve high accuracy, showing an outstanding accuracy of 96.83% in image classification.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.251-262
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• 2019

In this paper, we propose a simulator that provides various algorithms of RBF networks on neuromorphic chips. To develop algorithms based on neuromorphic chips, the disadvantages of using simulators are that it is difficult to test various types of algorithms, although time is fast. This proposed simulator can simulate four times more types of network architecture than existing simulators, and it provides an additional a two-layer structure algorithm in particular, unlike RBF networks provided by existing simulators. This two-layer architecture algorithm is configured to be utilized for multiple input data and compared to the existing RBF for performance analysis and validation of utilization. The analysis showed that the two-layer structure algorithm was more accurate than the existing RBF networks.

• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.47-57
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• 2021

Neuromorphic technology is proposed to complement the shortcomings of existing artificial intelligence technology by mimicking the human brain structure and computational process with hardware. NA-IDE has also been proposed for developing neuromorphic hardware-based IoT applications. To implement an SNN model in NA-IDE, commonly used input data must be transformed for use in the SNN model. In this paper, we implemented a neural coding method encoder component that converts image data into a spike train signal and uses it as an SNN input. The decoder component is implemented to convert the output back to image data when the SNN model generates a spike train signal. If the decoder component uses the same parameters as the encoding process, it can generate static data similar to the original data. It can be used in fields such as image-to-image and speech-to-speech to transform and regenerate input data using the proposed encoder and decoder.

• The Journal of the Convergence on Culture Technology
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• v.8 no.5
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• pp.613-618
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• 2022

Research on artificial intelligence based on SNN (Spiking Neural Networks) is drawing attention as a next-generation artificial intelligence that can overcome the limitations of artificial intelligence based on DNN (Deep Neural Networks) that is currently popular. In this paper, we describe the structure of the SNN compiler, a system SW that generate code from SNN description for neuromorphic computing systems. We also introduce the algorithms used for compiler implementation and present experimental results on how the execution time varies in neuromorphic computing systems depending on the the mapping algorithm. The mapping algorithm proposed in the text showed a performance improvement of up to 3.96 times over a random mapping. The results of this study will allow SNNs to be applied in various neuromorphic hardware.