• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.160-163
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• 1986

In a digital telecommunication network, the clock synchronization is inevitable to prevent the data loss caused by inconsistency of clock frequencies. This paper descries the considerations necessary for synchronization and the implementation of the clock synchronization system using digital processing phase locked loop method in TDX-1 switching system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.331-339
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• 2018

The IEEE 1588, commonly known as a precision time protocol (PTP), is a standard for precise clock synchronization that maintains networked measurements and control systems. The best master clock (BMC) algorithm is currently used to establish the master-slave hierarchy for PTP. The BMC allows a slave clock to automatically take over the duties of the master when the slave is disconnected due to a link failure and loses its synchronization; the slave clock depends on a timer to compensate for the failure of the master. However, the BMC algorithm does not provide a fast recovery mechanism in the case of a master failure. In this paper, we propose a technique that combines the IEEE 1588 with network bonding to provide a faster recovery mechanism in the case of a master failure. This technique is implemented by utilizing a pre-existing library PTP daemon (Ptpd) in Linux system, with a specific profile of the IEEE 1588 and it's controlled through bonding modes. Network bonding is a process of combining or joining two or more network interfaces together into a single interface. Network bonding offers performance improvements and redundancy. If one link fails, the other link will work immediately. It can be used in situations where fault tolerance, redundancy, or load balancing networks are needed. The results show combining IEEE 1588 with network bonding enables an incredible shorter recovery time than simply just relying on the IEEE 1588 recovery method alone.

• Journal of Life Science
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• v.27 no.10
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• pp.1225-1231
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• 2017

Disruptive expression patterns of the circadian clock genes are highly associated with many human diseases, including cancer. Cell cycle and proliferation is linked to a circadian rhythm; therefore, abnormal clock gene expression could result in tumorigenesis and malignant development. The molecular network of the circadian clock is based on transcriptional and translational feedback loops orchestrated by a variety of clock activators and clock repressors. The expression of 10~15% of the genome is controlled by the overall balance of circadian oscillation. Among the many clock genes, Period 1 (Per1) and Period 2 (Per2) are clock repressor genes that play an important role in the regulation of normal physiological rhythms. It has been reported that PER1 and PER2 are involved in the expression of cell cycle regulators including cyclins, cyclin-dependent kinases (CDKs), and CDK inhibitors. In addition, correlation of the down-regulation of PER1 and PER2 with development of many cancer types has been revealed. In this review, we focused on the molecular function of PER1 and PER2 in the circadian clock network and the transcriptional and translational targets of PER1 and PER2 involved in cell cycle and tumorigenesis. Moreover, we provide information suggesting that PER1 and PER2 could be promising therapeutic targets for cancer therapies and serve as potential prognostic markers for certain types of human cancers.

• Molecules and Cells
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• v.28 no.2
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• pp.75-80
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• 2009

The cyclic environmental conditions brought about by the 24 h rotation of the earth have allowed the evolution of endogenous circadian clocks that control the temporal alignment of behaviour and physiology, including the uptake and processing of nutrients. Both metabolic and circadian regulatory systems are built upon a complex feedback network connecting centres of the central nervous system and different peripheral tissues. Emerging evidence suggests that circadian clock function is closely linked to metabolic homeostasis and that rhythm disruption can contribute to the development of metabolic disease. At the same time, metabolic processes feed back into the circadian clock, affecting clock gene expression and timing of behaviour. In this review, we summarize the experimental evidence for this bimodal interaction, with a focus on the molecular mechanisms mediating this exchange, and outline the implications for clock-based and metabolic diseases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.123-132
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• 2014

In this paper, an IEEE1588 based clock synchronization technique for CAN (Controller Area Network) is presented. Clock synchronization plays a key role to the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipsets has been widely adopted for the synchronization of various industrial applications using Ethernet. However, there is no chipset available for CAN. This paper presents the implementation of IEEE1588 for CAN, which is implemented using only software and CAN packets without any dedicated chipset. The proposed approach is verified by the comparison between the estimated synchronization precision with a simple model and the measured precision with experimental setup.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.13-22
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• 2005

IEEE 802.11a is a standard for the high-speed wireless local area network (WLAN), supporting from 6 up to 54 Mbps in a 5 GHz band. We propose a channel equalization algerian and a sampling clock recovery algorithm by utilizing the Viterbi decoder output of the IEEE 802.11a WLAN standard. The proposed channel equalizer adaptively compensates channel variations. The proposed system uses re-encoded Viterbi decoder outputs as reference symbols for the adaptation of the channel equalizer. It also extracts sampling phase information with the Viterbi decoder outputs for fine adjustment of the sampling clock. The proposed sampling clock recovery and equalizer are more robust to noise and frequency selective fading environments than conventional systems using only four pilot samples.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.25 no.6_1
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• pp.537-543
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• 2007

Since the GPS absolute positioning with pseudorange measurements can significantly be affected by the observation error, the time series analysis of the GPS receiver clock errors was performed in this study. From the estimated receiver clock errors, the time series model is generated, and constrained back in the absolute positioning process. One of the CORS (Continuously Operating Reference Stations) network is used to analyze the behavior of the receiver clock. The dominant part of the model is the linear trend during 24 hours, and the seasonal component is also estimated. After constraining the modeled receiver clock errors, the estimated position error compared to the published coordinates is improved from ${\pm}11.4\;m\;to\;{\pm}9.5\;m$ in 3D RMS.